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r01ds0070ej0120 rev.1.20 page 1 of 112 jan 27, 2012 r32c/121 group renesas mcu r01ds0070ej0120 rev.1.20 jan 27, 2012 datasheet r32c/121 group datasheet 1. overview 1.1 features the m16c family offers a robust platform of 32-/16- bit cisc microcomputers (m cus) featuring high rom code efficiency, extensive emi/ems noise immunity, ultra-low power consumption, high-speed processing in actual applications, and numerous and varied integrated peripherals. extensive device scalability from low- to high-end, featuring a single architecture as well as compatib le pin assignments and peripheral functions, provides support for a vast range of application fields. the r32c/100 series is a high-end microcontroller series in the m16c family. with a 4-gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit cisc architecture, multiplier, multiply-accumulate unit, and floating point unit. the selection from the broadest choice of on- chip peripheral devices ? uart, crc, dmac, a/d and d/a converters, timers, i 2 c, and watchdog timer enables to minimize external components. the r32c/100 series, in particular, provides the r32c /121 group, a product specific to vehicle network. this product, provided as 100-pin plastic molded lqfp package, has two channels of can module, two channels of lin module, and standard peripherals. 1.1.1 applications automotive, audio, communication equipment, industrial equipment, etc.
r01ds0070ej0120 rev.1.20 page 2 of 112 jan 27, 2012 r32c/121 group 1. overview 1.1.2 performance overview tables 1.1 and 1.2 show the performanc e overview of the r32c/121 group. notes: 1. contact a renesas electronics sales office to use the non-e 2 dataflash version. 2. contact a renesas electronics sales office to use the optional features. table 1.1 performance overview (1/2) unit function explanation cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 15.625 ns (f(cpu) = 64 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 compatible fpu: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode memory flash memory: 128 to 512 kbytes ram: 12 to 32 kbytes data flash: 4 kbytes 2 blocks e 2 dataflash: none (1) /4 kbytes refer to table 1.3 for details voltage detector low voltage detector optional (2) low voltage detection interrupt clock clock generator ? 4 circuits (main cl ock, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main cl ock oscillator stop/restart detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 6, key input 4 interrupt priority levels: 7 watchdog timer 15 bits 1 (selectable input frequency from prescaler output) automatic timer start fu nction is available dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 46 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 characteristic transfer functions: immediate data transfer, calculation result transfer, chain transfer i/o ports programmable i/o ports ? 2 input-only ports ? 84 cmos i/o ports ? a pull-up resistor is selectable for every 4 input ports
r01ds0070ej0120 rev.1.20 page 3 of 112 jan 27, 2012 r32c/121 group 1. overview note: 1. contact a renesas electronics sales office to use the l version products. table 1.2 performance overview (2/2) unit function explanation timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart4 asynchronous/synchronous serial interface 5 channels ?i 2 c-bus (uart0 to uart2) ? special mode 2 (uart0 to uart2) a/d converter 10-bit resolution 26 channels sample and hold functionality integrated self test/open-circuit detection assist d/a converter 8-bit resolution 2 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 digital debounce circuit contained waveform generation (output compare): 16 bits 16 phase shift waveform output mode contained serial bus interface 3 channels ? synchronous serial communication mode ? 4-wire serial bus mode programmable character length: 8 to 16 bits lin module 2 channels can module 2 channels can functionality compliant with iso 11898-1 32 mailboxes flash memory programming and erasure supply voltage: vcc = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom co de protect, id code protect debugging: on-chip debug, on-board flash programming e 2 dataflash minimum endurance: 100, 000 program/erase cycles operating frequency/supply voltage 64 mhz/vcc = 3.0 to 5.5 v operating temperature -40c to 85c (j version) -40c to 105c (l version) (1) -40c to 125c (k version) current consumption 36 ma (vcc = 5.0 v, f(cpu) = 64 mhz) 8 a (vcc = 3.3 v, f(xcin) = 32.768 khz, wait mode) package 100-pin plastic molded lqfp (plqp0100kb-a)
r01ds0070ej0120 rev.1.20 page 4 of 112 jan 27, 2012 r32c/121 group 1. overview 1.2 product information table 1.3 lists the product information and figu re 1.1 shows the details of the part number. notes: 1. the old package code is as follows: plqp0100kb-a: 100p6q-a 2. ?+ 8 kbytes? in the rom capacity colu mn indicates the data flash capacity. 3. contact a renesas electronics sales office to use the non-e 2 dataflash version or the l version products. table 1.3 r32c/121 group product list as of january, 2012 part number package code (1) rom capacity (2) ram capacity e 2 dataflash remarks r5f64216jfb plqp0100kb-a 128 kbytes + 8 kbytes 12 kbytes 4 kbytes j version r5f64216lfb l version (3) r5f64216kfb k version r5f6421ajfb na (3) j version r5f6421alfb l version (3) r5f6421akfb k version r5f64217jfb 256 kbytes + 8 kbytes 20 kbytes 4 kbytes j version r5f64217lfb l version (3) r5f64217kfb k version r5f6421bjfb na (3) j version r5f6421blfb l version (3) r5f6421bkfb k version r5f64218jfb 384 kbytes + 8 kbytes 24 kbytes 4 kbytes j version r5f64218lfb l version (3) r5f64218kfb k version r5f6421cjfb na (3) j version r5f6421clfb l version (3) r5f6421ckfb k version R5F64219JFB 512 kbytes + 8 kbytes 32 kbytes 4 kbytes j version r5f64219lfb l version (3) r5f64219kfb k version r5f6421djfb na (3) j version r5f6421dlfb l version (3) r5f6421dkfb k version
r01ds0070ej0120 rev.1.20 page 5 of 112 jan 27, 2012 r32c/121 group 1. overview figure 1.1 part numbering part number r5 f 64 21 7 j xxx fb package code fb : plqp0100kb-a rom number omitted in the flash memory version memory type f : flash memory version r32c/121 group r32c/100 series rom/ram/e 2 dataflash capacity 6 : 128 kb/12 kb/4 kb 7 : 256 kb/20 kb/4 kb 8 : 384 kb/24 kb/4 kb 9 : 512 kb/32 kb/4 kb a : 128 kb/12 kb/none b : 256 kb/20 kb/none c : 384 kb/24 kb/none d : 512 kb/32 kb/none temperature code j : -40c to 85c l : -40c to 105c k : -40c to 125c
r01ds0070ej0120 rev.1.20 page 6 of 112 jan 27, 2012 r32c/121 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram of the r32c/121 group. figure 1.2 r32c/121 group block diagram port p0 port p1 port p2 port p3 port p4 port p5 port p6 8 8 8 8 8 8 8 port p7 p8_5 port p9 8 7 5 port p8 port p10 8 p9_1 clock generator: 4 circuits - xin-xout - xcin-xcout - on-chip oscillator - pll frequency synthesizer watchdog timer: 15 bits dmac dmac ii x-y converter: 16 bits 16 bits crc calculator (ccitt) x 16 + x 12 + x 5 + 1 a/d converter: 10 bits 1 circuit 26 inputs serial interface: 5 channels d/a converter: 8 bits 2 channels r32c/100 series cpu core r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb flg intb isp usp pc svf svp vct memory rom ram multiplier floating-point unit r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb serial bus interface: 3 channel can module: 2 channel lin module: 2 channels e 2 dataflash intelligent i/o time measurement: 16 wave generation: 16 timer: timer a 16 bits 5 timers timer b 16 bits 6 timers three-phase motor controller peripheral functions
r01ds0070ej0120 rev.1.20 page 7 of 112 jan 27, 2012 r32c/121 group 1. overview 1.4 pin assignment figure 1.3 shows the pin assignment (top view) and tables 1.4 to 1.6 show the pin characteristics. figure 1.3 pin assignment (top view) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 88 73 rxd4 / tb2in / adtrg / p9_7 p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / sso2 p6_7 / txd1 / sda1 / srxd1 / sso1 avcc / vcc vref an_0 / p10_0 avss an_1 / p10_1 an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 an0_0 / p0_0 an0_1 / p0_1 an0_2 / p0_2 an0_3 / p0_3 an0_4 / p0_4 an0_5 / p0_5 an0_6 / p0_6 an0_7 / p0_7 p6_6 / rxd1 / scl1 / stxd1 / ssi1 p6_5 / clk1 / ssck1 p6_4 / cts1 / rts1 / ss1 / scs1 p6_3 / tb5in / txd0 / sda0 / srxd0 / sso0 p6_2 / tb2in / rxd0 / scl0 / stxd0 / ssi0 p6_1 / tb1in / clk0 / ssck0 p6_0 / tb0in / cts0 / rts0 / ss0 / scs0 p5_7 / iio0_7 / scs2 p5_6 / iio0_6 / ssi2 p5_5 / iio0_5 / ssck2 p5_4 / iio0_4 / sso2 p5_3 / clkout / iio0_3 p5_2 / iio0_2 p5_1 / iio0_1 p5_0 / iio0_0 p4_7 / iio1_7 / scs1 / lin1in p4_6 / iio1_6 / ssi1 / lin1out p4_5 / iio1_5 / ssck1 / lin0in p4_4 / iio1_4 / sso1 / lin0out can1out / txd4 / anex1 / p9_6 can1in / can1wu / clk4 / anex0 / p9_5 cts4 / rts4 / tb4in / da1 / p9_4 vdc0 p9_1 vdc1 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc nmi / p8_5 int2 / p8_4 can0in / can0wu / can1in / can1wu / int1 / p8_3 can0out / can1out / int0 / p8_2 lin1out / iio1_5 / ud0b / ud1b / cts3 / rts3 / u / ta3out / ta4in / p8_1 lin1in / ud0a / ud1a / rxd3 / u / ta4out / p8_0 can0in / can0wu / iio1_4 / ud0b / ud1b / clk3 / ta3in / p7_7 can0out / iio1_3 / ud0a / ud1a / txd3 / ta3out / p7_6 lin0in / iio1_2 / w / ta2in / p7_5 lin0out / iio1_1 / w / ta2out / p7_4 scs2 / iio1_0 / cts2 / rts2 / ss2 / v / ta1in / p7_3 p7_2 / ta1out / v / clk2 / ssck2 p7_1 / ta0in / tb5in / rxd2 / scl2 / stxd2 / iio1_7 / ssi2 tb3in / da0 / p9_3 ssck0 / iio0_1 / iio1_1 / p1_1 ssi0 / iio0_2 / iio1_2 / p1_2 p1_3 / iio0_3 / iio1_3 / scs0 p1_4 / tb0in / iio0_4 / iio1_4 p1_5 / int3 / iio0_5 / iio1_5 p1_6 / int4 / iio0_6 / iio1_6 p1_7 / int5 / iio0_7 / iio1_7 p2_0 / an2_0 vss p3_0 / ta0out / ud0a / ud1a / lin0out vcc p3_1 / ta3out / ud0b / ud1b / lin0in p3_2 / ta1out / v / lin1out p3_3 / ta1in / v / lin1in p3_4 / ta2out / w / clk4 p3_5 / ta2in / w / rxd4 p3_6 / ta4out / u / txd4 p3_7 / ta4in / tb1in / u / cts4 / rts4 p4_0 / cts3 / rts3 / iio1_0 p4_1 / clk3 / iio1_1 p4_2 / rxd3 / iio1_2 p4_3 / txd3 / iio1_3 p2_1 / an2_1 p2_2 / an2_2 p2_3 / an2_3 p2_4 / an2_4 p2_5 / an2_5 p2_6 / an2_6 p2_7 / an2_7 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 sso0 / iio0_0 / iio1_0 / p1_0 r32c/121 group plqp0100kb-a (100p6q-a) (top view) (note 1) note: 1. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?.
r01ds0070ej0120 rev.1.20 page 8 of 112 jan 27, 2012 r32c/121 group 1. overview table 1.4 pin characteristics (1/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin lin / can module pin analog pin 1p9_4 tb4in cts4 / rts4 da1 2p9_3 tb3in da0 3 vdc0 4p9_1 5 vdc1 6nsd 7cnvss 8xcinp8_7 9 xcout p8_6 10 reset 11 xout 12 vss 13 xin 14 vcc 15 p8_5 nmi 16 p8_4 int2 17 p8_3 int1 can0in/ can0wu / can1in/ can1wu 18 p8_2 int0 can0out/ can1out 19 p8_1 ta3out/ ta4in/ u cts3 / rts3 iio1_5/ud0b/ud1b lin1out 20 p8_0 ta4out/u rxd3 ud0a/ud1a lin1in 21 p7_7 ta3in clk3 iio1_4/ud0b/ud1b can0in/ can0wu 22 p7_6 ta3out txd3 iio1_3/ud0a/ud1a can0out 23 p7_5 ta2in/ w iio1_2 lin0in 24 p7_4 ta2out/w iio1_1 lin0out 25 p7_3 ta1in/ vcts2 / rts2 / ss2 / scs2 iio1_0 26 p7_2 ta1out/v clk2/ssck2 27 p7_1 ta0in/ tb5in rxd2/scl2/stxd2/ ssi2 iio1_7 28 p7_0 ta0out txd2/sda2/ srxd2/sso2 iio1_6 29 p6_7 txd1/sda1/ srxd1/sso1 30 p6_6 rxd1/scl1/stxd1/ ssi1 31 p6_5 clk1/ssck1 32 p6_4 cts1 / rts1 / ss1 / scs1 33 p6_3 tb5in txd0/sda0/ srxd0/sso0 34 p6_2 tb2in rxd0/scl0/stxd0/ ssi0
r01ds0070ej0120 rev.1.20 page 9 of 112 jan 27, 2012 r32c/121 group 1. overview table 1.5 pin characteristics (2/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin lin / can module pin analog pin 35 p6_1 tb1in clk0/ssck0 36 p6_0 tb0in cts0 / rts0 / ss0 / scs0 37 p5_7 scs2 iio0_7 38 p5_6 ssi2 iio0_6 39 p5_5 ssck2 iio0_5 40 p5_4 sso2 iio0_4 41 clkout p5_3 iio0_3 42 p5_2 iio0_2 43 p5_1 iio0_1 44 p5_0 iio0_0 45 p4_7 scs1 iio1_7 lin1in 46 p4_6 ssi1 iio1_6 lin1out 47 p4_5 ssck1 iio1_5 lin0in 48 p4_4 sso1 iio1_4 lin0out 49 p4_3 txd3 iio1_3 50 p4_2 rxd3 iio1_2 51 p4_1 clk3 iio1_1 52 p4_0 cts3 / rts3 iio1_0 53 p3_7 ta4in/ u / tb1in cts4 / rts4 54 p3_6 ta4out/u txd4 55 p3_5 ta2in/ w rxd4 56 p3_4 ta2out/w clk4 57 p3_3 ta1in/ v lin1in 58 p3_2 ta1out/v lin1out 59 p3_1 ta3out ud0b/ud1b lin0in 60 vcc 61 p3_0 ta0out ud0a/ud1a lin0out 62 vss 63 p2_7 an2_7 64 p2_6 an2_6 65 p2_5 an2_5 66 p2_4 an2_4 67 p2_3 an2_3 68 p2_2 an2_2 69 p2_1 an2_1 70 p2_0 an2_0 71 p1_7 int5 iio0_7/iio1_7 72 p1_6 int4 iio0_6/iio1_6 73 p1_5 int3 iio0_5/iio1_5 74 p1_4 tb0in iio0_4/iio1_4
r01ds0070ej0120 rev.1.20 page 10 of 112 jan 27, 2012 r32c/121 group 1. overview table 1.6 pin characteristics (3/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin lin / can module pin analog pin 75 p1_3 scs0 iio0_3/iio1_3 76 p1_2 ssi0 iio0_2/iio1_2 77 p1_1 ssck0 iio0_1/iio1_1 78 p1_0 sso0 iio0_0/iio1_0 79 p0_7 an0_7 80 p0_6 an0_6 81 p0_5 an0_5 82 p0_4 an0_4 83 p0_3 an0_3 84 p0_2 an0_2 85 p0_1 an0_1 86 p0_0 an0_0 87 p10_7 ki3 an_7 88 p10_6 ki2 an_6 89 p10_5 ki1 an_5 90 p10_4 ki0 an_4 91 p10_3 an_3 92 p10_2 an_2 93 p10_1 an_1 94 avss 95 p10_0 an_0 96 vref 97 avcc/ vcc 98 p9_7 tb2in rxd4 adtrg 99 p9_6 txd4 can1out anex1 100 p9_5 clk4 can1in/ can1wu anex0
r01ds0070ej0120 rev.1.20 page 11 of 112 jan 27, 2012 r32c/121 group 1. overview 1.5 pin definitions and functions tables 1.7 to 1.9 show the pin definitions and functions. table 1.7 pin definitions and functions (1/3) function symbol i/o description power supply vcc, vss i applicable as fo llows: vcc = 3.0 to 5.5 v, vss = 0 v connecting pins for decoupling capacitor vdc0, vdc1 ? a decoupling capacitor for internal voltage should be connected between vdc0 and vdc1 analog power supply avcc, avss i power supply for the a/d converter. avss should be connected to vss reset input reset i the mcu is reset when this pin is driven low cnvss cnvss i this pin should be connected to vss via a resistor. debug port nsd i/o this pin is to communicate with a debugger. it should be connected to vcc via a resistor of 1 to 4.7 k main clock input xin i input/output for the main cl ock oscillator. a crystal, or a ceramic resonator should be connected between pins xin and xout. an external clock should be input at the xin while leaving the xout open main clock output xout o sub clock input xcin i input/output for the sub clock osc illator. a crystal oscillator should be connec ted between pins xcin and xcout. an external clock should be input at the xcin while leaving the xcout open sub clock output xcout o clock output clkout o output of the clock with the same frequency as low speed clocks, f8, or f32 external interrupt input int0 to int5 i input for external interrupts nmi input p8_5/nmi i input for nmi key input interrupt ki0 to ki3 i input for the key input interrupt i/o ports p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i/o i/o ports in cmos. each port can be programmed to input or output under the control of the direction register. pull-up resistors are selected for the following 4-pin units, but are enabled only for the input pins: pi_0 to pi_3 and pi_4 to pi_7 (i = 0 to 10) input port p9_1 i input port in cmos. pull-up resistors are selectable for p9_1 and p9_3
r01ds0070ej0120 rev.1.20 page 12 of 112 jan 27, 2012 r32c/121 group 1. overview table 1.8 pin definitions and functions (2/3) function symbol i/o description timer a ta0out to ta4out i/o timers a0 to a4 input/output ta0in to ta4in i timers a0 to a4 input timer b tb0in to tb5in i timers b0 to b5 input three-phase motor control timer output u, u , v, v , w, w o three-phase motor control timer output serial interface cts0 to cts4 i handshake input rts0 to rts4 o handshake output clk0 to clk4 i/o transmit/receive clock input/output rxd0 to rxd4 i serial data input txd0 to txd4 o serial data output i 2 c bus (simplified) sda0 to sda2 i/o serial data input/output scl0 to scl2 i/o transmit/receive clock input/output serial interface special functions stxd0 to stxd2 o serial data output in slave mode srxd0 to srxd2 i serial da ta input in slave mode ss0 to ss2 i input to control serial interface special functions a/d converter an_0 to an_7, an0_0 to an0_7, an2_0 to an2_7 i analog input for the a/d converter adtrg i external trigger input for the a/d converter anex0 i/o expanded analog input for the a/d converter and output in external op-amp connection mode anex1 i expanded analog input for the a/d converter d/a converter da0, da1 o out put for the d/a converter reference voltage input vref i reference voltage input for the a/d converter and d/ a converter
r01ds0070ej0120 rev.1.20 page 13 of 112 jan 27, 2012 r32c/121 group 1. overview table 1.9 pin definitions and functions (3/3) function symbol i/o description intelligent i/o iio0_0 to iio0_7 i/o input/output for the intell igent i/o group 0. either input capture or output compare is selectable iio1_0 to iio1_7 i/o input/output for the intell igent i/o group 1. either input capture or output compare is selectable ud0a, ud0b, ud1a, ud1b i input for the two-phase encoder serial bus interface sso0 to sso2 i/o serial data output. functions as serial data input/ output in 4-wire serial bus mode ssi0 to ssi2 i/o serial data input. functions as serial data input/ output in 4-wire serial bus mode ssck0 to ssck2 i/o transmit/receive clock input/output scs0 to scs2 i/o input/output to control the synchronous serial interface lin module lin0out, lin1out o transmit da ta output for the lin communications lin0in, lin1in i receive data input for the lin communications can module can0in, can1in i receive da ta input for the can communications can0out, can1out o transmit data output for the can communications can0wu , can1wu i input for the can wake-up interrupt
r01ds0070ej0120 rev.1.20 page 14 of 112 jan 27, 2012 r32c/121 group 2. central processing unit (cpu) 2. central processi ng unit (cpu) the cpu contains the registers shown below. there ar e two register banks each consisting of registers r2r0, r3r1, r6r4, r7r5, a0 to a3, sb, and fb. figure 2.1 cpu registers dda0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dcr0 dct0 dmd0 b0 b31 vct svp svf pc intb usp isp fb sb a3 a2 a1 r5 r7 r6 r4 r1l r1h r3l r3h r2h r2l r0h r0l a0 flg b0 b31 general purpose registers fast interrupt registers dmac-associated registers (2) notes: 1. there are two banks of these registers. 2. there are four identical sets of dmac-associated registers. dma destination address reload register flag register data registers (1) address registers (1) static base register (1) frame base register (1) user stack pointer interrupt stack pointer interrupt vector table base register program counter save flag register save pc register vector register r2r0 r3r1 r6r4 r7r5 dma source address register dma source address reload register dma terminal count reload register dma terminal count register dma mode register c d z s b o i u ipl rnd b0 b31 b8 b7 b16 b15 b0 b31 b23 b15 b7 dma destination address register blank spaces are reserved. fu fo dp b24 b23 b23
r01ds0070ej0120 rev.1.20 page 15 of 112 jan 27, 2012 r32c/121 group 2. central processing unit (cpu) 2.1 general purpose registers 2.1.1 data registers (r2r0, r3r1, r6r4, and r7r5) these 32-bit registers are pr imarily used for transfers an d arithmetic/logic operations. each of the registers can be divided into upper and lo wer 16-bit registers, e.g. r2r0 can be divided into r2 and r0, r3r1 can be divided into r3 and r1, etc. moreover, data registers r2r0 and r3r1 can be divided into four 8-bit data registers: upper (r2h and r3h), mid-upper (r2l and r3l), mid-lower (r0h and r1h), and lower (r0l and r1l). 2.1.2 address registers (a0, a1, a2, and a3) these 32-bit registers have functions similar to data registers. they are also used for address register indirect addressing and address register relative addressing. 2.1.3 static base register (sb) this 32-bit register is us ed for sb relative addressing. 2.1.4 frame base register (fb) this 32-bit register is used for fb relative addressing. 2.1.5 program counter (pc) this 32-bit counter indicates the address of the instruction to be executed next. 2.1.6 interrupt vector ta ble base register (intb) this 32-bit register indicates the star t address of a relocatable vector table. 2.1.7 user stack pointer (usp) a nd interrupt stack pointer (isp) two types of 32-bit stack pointers (sps) are provi ded: user stack pointer (usp) and interrupt stack pointer (isp). use the stack pointer select flag (u flag) to select either the user stack poin ter (usp) or the interrupt stack pointer (isp). the u flag is bit 7 in the flag register (flg). refer to 2.1.8 ?flag register (flg)? for details. to minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer (usp) or the interrupt stack pointer (isp) to a multiple of 4. 2.1.8 flag register (flg) this 32-bit register indicates the cpu status. 2.1.8.1 carry flag (c flag) this flag retains a carry, borrow, or shifted-ou t bit generated by the arithmetic logic unit (alu). 2.1.8.2 debug flag (d flag) this flag is only for debugging. only set this bit to 0. 2.1.8.3 zero flag (z flag) this flag becomes 1 when the result of an operation is 0; otherwise it is 0. 2.1.8.4 sign flag (s flag) this flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
r01ds0070ej0120 rev.1.20 page 16 of 112 jan 27, 2012 r32c/121 group 2. central processing unit (cpu) 2.1.8.5 register bank se lect flag (b flag) this flag selects a register bank. it indicates 0 w hen register bank 0 is selected, and 1 when register bank 1 is selected. 2.1.8.6 overflow flag (o flag) this flag becomes 1 when the result of an operation overflows; otherwise it is 0. 2.1.8.7 interrupt enab le flag (i flag) this flag enables maskable interrupts. to disable mask able interrupts, set this flag to 0. to enable them, set this flag to 1. when an in terrupt is accepted, the flag becomes 0. 2.1.8.8 stack pointer se lect flag (u flag) to select the interrupt stack pointer (isp), set this flag to 0. to select the user stack pointer (usp), set this flag to 1. it becomes 0 when a hardware interrupt is accepted or when an int instruction designated by a software interrupt number from 0 to 127 is executed. 2.1.8.9 floating-point u nderflow flag (fu flag) this flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.10 floating-point o verflow flag (fo flag) this flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.11 processor interrup t priority level (ipl) the processor interrupt priority le vel (ipl), consisting of 3 bits, se lects a processor interrupt priority level from level 0 to 7. an interrupt is enabled when the interrupt request level is higher than the selected ipl. when the processor interrupt priority level (ipl) is set to 111b (level 7), all interrupts are disabled. 2.1.8.12 fixed-point radix po int designation bit (dp bit) this bit designates the radix point. it also specifies which portion of the fixed-point multiplication result to extract. it is used for the mulx instruction. 2.1.8.13 floating-point rounding mode (rnd) the 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results. 2.1.8.14 reserved only set this bit to 0. the read value is undefined.
r01ds0070ej0120 rev.1.20 page 17 of 112 jan 27, 2012 r32c/121 group 2. central processing unit (cpu) 2.2 fast interrupt registers the following three registers are provided to mi nimize the overhead of the interrupt sequence. 2.2.1 save flag register (svf) this 32-bit register is used to save the flag register when a fast interrupt is generated. 2.2.2 save pc register (svp) this 32-bit register is used to save the prog ram counter when a fast interrupt is generated. 2.2.3 vector register (vct) this 32-bit register is used to indicate a ju mp address when a fast interrupt is generated. 2.3 dmac-associated registers there are seven types of dmac-associated registers. 2.3.1 dma mode registers (d md0, dmd1, dmd2, and dmd3) these 32-bit registers are used to set dma transfer mode, bit rate, etc. 2.3.2 dma terminal count register s (dct0, dct1, dct2, and dct3) these 24-bit registers are used to set the number of dma transfers. 2.3.3 dma terminal count reload regi sters (dcr0, dcr1 , dcr2, and dcr3) these 24-bit registers are used to set the relo aded values for dma terminal count registers. 2.3.4 dma source address register s (dsa0, dsa1, dsa2, and dsa3) these 32-bit registers are used to set dma source addresses. 2.3.5 dma source address reload regi sters (dsr0, dsr1, dsr2, and dsr3) these 32-bit registers are used to set the relo aded values for dma source address registers. 2.3.6 dma destination a ddress registers (dda0, dda1, dda2, and dda3) these 32-bit registers are used to set dma destination addresses. 2.3.7 dma destination address reload registers (ddr0, ddr1, ddr2, and ddr3) these 32-bit registers are used to set reloaded values for dma destination address registers.
r01ds0070ej0120 rev.1.20 page 18 of 112 jan 27, 2012 r32c/121 group 3. memory 3. memory figure 3.1 shows the memory map of the r32c/121 group. the r32c/121 group provides a 4-gbyte address space from 00000000h to ffffffffh. the internal rom is mapped from address ffffffffh in the inferior direction. for example, the 512-kbyte internal rom is mapped from fff80000h to ffffffffh. the fixed interrupt vector table contains the start address of interrupt handlers and is mapped from ffffffdch to ffffffffh. the internal ram is mapped from address 00000400h in the superior direction. for example, the 32-kbyte internal ram is mapped from 00000400h to 000083ffh. besides being used for data storage, the internal ram functions as a stack(s) for subrout ine calls and/or interrupt handlers. special function registers (sfrs), which are contro l registers for peripheral functions, are mapped from 00000000h to 000003ffh, and from 00040000h to 0004ffffh. unoccupied sfr locations are reserved, and no access is allowed. figure 3.1 memory map internal ram sfr1 sfr2 internal rom 00000000h ffffffffh reset nmi reserved watchdog timer (2) reserved reserved brk instruction overflow undefined instruction ffffffffh ffffffdch notes: 1. the flash memory version provides two additional 4-kbyte spaces (blocks a and b) for storing data. 2. the watchdog timer interrupt shares a vector with the oscillator stop detection interrupt and low voltage detection interrupt. yyyyyyyyh 00000400h xxxxxxxxh reserved 00040000h internal rom (data space) (1) 00060000h 00062000h reserved 00050000h reserved internal ram capacity xxxxxxxxh 32 kbytes 00008400h 24 kbytes 00006400h 12 kbytes 00003400h internal rom capacity yyyyyyyyh 128 kbytes fffe0000h 256 kbytes fffc0000h 384 kbytes fffa0000h 512 kbytes fff80000h 20 kbytes 00005400h
r01ds0070ej0120 rev.1.20 page 19 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) 4. special function registers (sfrs) sfrs are memory-mapped peripheral registers that c ontrol the operation of peripherals. table 4.1 sfr list (1) to table 4.56 sfr list (56) list the sfr details. table 4.1 sfr list (1) address register symbol reset value 000000h 000001h 000002h 000003h 000004h clock control register ccr 0001 1000b 000005h 000006h flash memory control register fmcr 0000 0001b 000007h protect release register prr 00h 000008h 000009h 00000ah 00000bh 00000ch 00000dh 00000eh 00000fh 000010h 000011h 000012h 000013h 000014h 000015h 000016h 000017h 000018h 000019h 00001ah 00001bh 00001ch flash memory rewrite bus control register febc 0000h 00001dh 00001eh peripheral bus control register pbc 0504h 00001fh 000020h to 00005fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 20 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.2 sfr list (2) address register symbol reset value 000060h 000061h timer b5 interrupt control register tb5ic xxxx x000b 000062h 000063h uart2 receive/ack interrupt control register s2ric xxxx x000b 000064h 000065h 000066h 000067h 000068h dma0 transfer complete interr upt control register dm0ic xxxx x000b 000069h uart0 start condition/stop condition detection interrupt control register bcn0ic xxxx x000b 00006ah dma2 transfer complete interr upt control register dm2ic xxxx x000b 00006bh a/d converter 0 convert comple tion interrupt control register ad0ic xxxx x000b 00006ch timer a0 interrupt co ntrol register ta0ic xxxx x000b 00006dh intelligent i/o interrupt c ontrol register 0 iio0ic xxxx x000b 00006eh timer a2 interrupt control register ta2ic xxxx x000b 00006fh intelligent i/o interrupt c ontrol register 2 iio2ic xxxx x000b 000070h timer a4 interrupt control register ta4ic xxxx x000b 000071h intelligent i/o interrupt c ontrol register 4 iio4ic xxxx x000b 000072h uart0 receive/ack interrupt control register s0ric xxxx x000b 000073h intelligent i/o interrupt c ontrol register 6 iio6ic xxxx x000b 000074h uart1 receive/ack interrupt control register s1ric xxxx x000b 000075h intelligent i/o interrupt c ontrol register 8 iio8ic xxxx x000b 000076h timer b1 interrupt control register tb1ic xxxx x000b 000077h intelligent i/o interrupt cont rol register 10 iio10ic xxxx x000b 000078h timer b3 interrupt control register tb3ic xxxx x000b 000079h 00007ah int5 interrupt control register int5ic xx00 x000b 00007bh can0 wake-up interrupt control register c0wic xxxx x000b 00007ch int3 interrupt control register int3ic xx00 x000b 00007dh 00007eh int1 interrupt control register int1ic xx00 x000b 00007fh lin low detection interrupt control register lldic xxxx x000b 000080h 000081h uart2 transmit/nack interrupt control register s2tic xxxx x000b 000082h 000083h 000084h 000085h 000086h 000087h uart2 start condition/stop condition detection interrupt control register bcn2ic xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 21 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.3 sfr list (3) address register symbol reset value 000088h dma1 transfer complete interr upt control register dm1ic xxxx x000b 000089h uart1 start condition/stop condition detection interrupt control register bcn1ic xxxx x000b 00008ah dma3 transfer complete interr upt control register dm3ic xxxx x000b 00008bh key input interrupt control register kupic xxxx x000b 00008ch timer a1 interrupt co ntrol register ta1ic xxxx x000b 00008dh intelligent i/o interrupt c ontrol register 1 iio1ic xxxx x000b 00008eh timer a3 interrupt control register ta3ic xxxx x000b 00008fh intelligent i/o interrupt c ontrol register 3 iio3ic xxxx x000b 000090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 000091h intelligent i/o interrupt c ontrol register 5 iio5ic xxxx x000b 000092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 000093h intelligent i/o interrupt c ontrol register 7 iio7ic xxxx x000b 000094h timer b0 interrupt control register tb0ic xxxx x000b 000095h intelligent i/o interrupt c ontrol register 9 iio9ic xxxx x000b 000096h timer b2 interrupt control register tb2ic xxxx x000b 000097h intelligent i/o interrupt cont rol register 11 iio11ic xxxx x000b 000098h timer b4 interrupt control register tb4ic xxxx x000b 000099h 00009ah int4 interrupt control register int4ic xx00 x000b 00009bh can1 wake-up interrupt control register c1wic xxxx x000b 00009ch int2 interrupt control register int2ic xx00 x000b 00009dh 00009eh int0 interrupt control register int0ic xx00 x000b 00009fh 0000a0h intelligent i/o interrupt requ est register 0 iio0ir 0000 0xx1b 0000a1h intelligent i/o interrupt requ est register 1 iio1ir 0000 0xx1b 0000a2h intelligent i/o interrupt requ est register 2 iio2ir 0000 0x01b 0000a3h intelligent i/o interrupt requ est register 3 iio3ir 0000 0xx1b 0000a4h intelligent i/o interrupt requ est register 4 iio4ir 000x 0xx1b 0000a5h intelligent i/o interrupt r equest register 5 iio5ir 0000 00x1b 0000a6h intelligent i/o interrupt r equest register 6 iio6ir 0000 00x1b 0000a7h intelligent i/o interrupt requ est register 7 iio7ir 000x 00x1b 0000a8h intelligent i/o interrupt r equest register 8 iio8ir 0000 00x1b 0000a9h intelligent i/o interrupt r equest register 9 iio9ir 0000 00x1b 0000aah intelligent i/o interrupt requ est register 10 iio10ir 0000 00x1b 0000abh intelligent i/o interrupt requ est register 11 iio11ir 0000 00x1b 0000ach 0000adh 0000aeh 0000afh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 22 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.4 sfr list (4) address register symbol reset value 0000b0h intelligent i/o interrupt enable register 0 iio0ie 00h 0000b1h intelligent i/o interrupt enable register 1 iio1ie 00h 0000b2h intelligent i/o interrupt enable register 2 iio2ie 00h 0000b3h intelligent i/o interrupt enable register 3 iio3ie 00h 0000b4h intelligent i/o interrupt enable register 4 iio4ie 00h 0000b5h intelligent i/o interrupt enable register 5 iio5ie 00h 0000b6h intelligent i/o interrupt enable register 6 iio6ie 00h 0000b7h intelligent i/o interrupt enable register 7 iio7ie 00h 0000b8h intelligent i/o interrupt enable register 8 iio8ie 00h 0000b9h intelligent i/o interrupt enable register 9 iio9ie 00h 0000bah intelligent i/o interrupt enable register 10 iio10ie 00h 0000bbh intelligent i/o interrupt enable register 11 iio11ie 00h 0000bch 0000bdh 0000beh 0000bfh 0000c0h serial bus interf ace 0 interrupt contro l register ss0ic xxxx x000b 0000c1h can0 transmit interrupt control r egister c0tic xxxx x000b 0000c2h serial bus interf ace 2 interrupt contro l register ss2ic xxxx x000b 0000c3h can0 error interrupt co ntrol register c0eic xxxx x000b 0000c4h 0000c5h can1 receive interrupt control r egister c1ric xxxx x000b 0000c6h 0000c7h 0000c8h 0000c9h 0000cah 0000cbh 0000cch 0000cdh 0000ceh 0000cfh 0000d0h can0 transmit fi fo interrupt co ntrol register c0ftic xxxx x000b 0000d1h 0000d2h can1 transmit fi fo interrupt co ntrol register c1ftic xxxx x000b 0000d3h 0000d4h 0000d5h lin0 interrupt cont rol register l0ic xxxx x000b 0000d6h 0000d7h 0000d8h e 2 dataflash interrupt control register e2fic xxxx x000b 0000d9h 0000dah 0000dbh 0000dch 0000ddh uart3 transmit interrupt control register s3tic xxxx x000b 0000deh 0000dfh uart4 transmit interrupt control register s4tic xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 23 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.5 sfr list (5) address register symbol reset value 0000e0h serial bus interface 1 interrupt control register ss1ic xxxx x000b 0000e1h can0 receive interrupt control register c0ric xxxx x000b 0000e2h 0000e3h can1 transmit interrupt control register c1tic xxxx x000b 0000e4h 0000e5h can1 error interrupt control register c1eic xxxx x000b 0000e6h 0000e7h 0000e8h 0000e9h 0000eah 0000ebh 0000ech 0000edh 0000eeh 0000efh 0000f0h can0 receive fi fo interrupt control register c0fric xxxx x000b 0000f1h 0000f2h can1 receive fi fo interrupt control register c1fric xxxx x000b 0000f3h 0000f4h 0000f5h lin1 interr upt control register l1ic xxxx x000b 0000f6h 0000f7h 0000f8h 0000f9h 0000fah 0000fbh 0000fch 0000fdh uart3 receive interrupt control r egister s3ric xxxx x000b 0000feh 0000ffh uart4 receive interrupt control register s4ric xxxx x000b 000100h group 1 time measurement/waveform generation register 0 g1tm0/g1po0 xxxxh 000101h 000102h group 1 time measurement/waveform generation register 1 g1tm1/g1po1 xxxxh 000103h 000104h group 1 time measurement/waveform generation register 2 g1tm2/g1po2 xxxxh 000105h 000106h group 1 time measurement/waveform generation register 3 g1tm3/g1po3 xxxxh 000107h x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 24 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.6 sfr list (6) address register symbol reset value 000108h group 1 time measurement/waveform generation register 4 g1tm4/g1po4 xxxxh 000109h 00010ah group 1 time measurement/waveform generation register 5 g1tm5/g1po5 xxxxh 00010bh 00010ch group 1 time measur ement/waveform generation register 6 g1tm6/g1po6 xxxxh 00010dh 00010eh group 1 time measurement/waveform generation register 7 g1tm7/g1po7 xxxxh 00010fh 000110h group 1 waveform generation control register 0 g1pocr0 0000 x000b 000111h group 1 waveform generation control register 1 g1pocr1 0x00 x000b 000112h group 1 waveform generation control register 2 g1pocr2 0x00 x000b 000113h group 1 waveform generation control register 3 g1pocr3 0x00 x000b 000114h group 1 waveform generation control register 4 g1pocr4 0x00 x000b 000115h group 1 waveform generation control register 5 g1pocr5 0x00 x000b 000116h group 1 waveform generation control register 6 g1pocr6 0x00 x000b 000117h group 1 waveform generation control register 7 g1pocr7 0x00 x000b 000118h group 1 time measurement control register 0 g1tmcr0 00h 000119h group 1 time measurement control register 1 g1tmcr1 00h 00011ah group 1 time measurement control register 2 g1tmcr2 00h 00011bh group 1 time measurement control register 3 g1tmcr3 00h 00011ch group 1 time measurement control register 4 g1tmcr4 00h 00011dh group 1 time measurement control register 5 g1tmcr5 00h 00011eh group 1 time measurement control register 6 g1tmcr6 00h 00011fh group 1 time measurement control register 7 g1tmcr7 00h 000120h group 1 base timer register g1bt xxxxh 000121h 000122h group 1 base timer control register 0 g1bcr0 0000 0000b 000123h group 1 base timer control register 1 g1bcr1 0000 0000b 000124h group 1 time measurement prescaler register 6 g1tpr6 00h 000125h group 1 time measurement prescaler register 7 g1tpr7 00h 000126h group 1 function enable register g1fe 00h 000127h group 1 function select register g1fs 00h 000128h 000129h 00012ah 00012bh 00012ch 00012dh 00012eh 00012fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 25 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.7 sfr list (7) address register symbol reset value 000130h to 00016fh 000170h 000171h 000172h 000173h 000174h 000175h 000176h 000177h 000178h 000179h 00017ah 00017bh 00017ch 00017dh 00017eh 00017fh 000180h group 0 time measurement/waveform generation register 0 g0tm0/g0po0 xxxxh 000181h 000182h group 0 time measurement/waveform generation register 1 g0tm1/g0po1 xxxxh 000183h 000184h group 0 time measurement/waveform generation register 2 g0tm2/g0po2 xxxxh 000185h 000186h group 0 time measurement/waveform generation register 3 g0tm3/g0po3 xxxxh 000187h 000188h group 0 time measurement/waveform generation register 4 g0tm4/g0po4 xxxxh 000189h 00018ah group 0 time measurement/waveform generation register 5 g0tm5/g0po5 xxxxh 00018bh 00018ch group 0 time measur ement/waveform generation register 6 g0tm6/g0po6 xxxxh 00018dh 00018eh group 0 time measurement/waveform generation register 7 g0tm7/g0po7 xxxxh 00018fh 000190h group 0 waveform generation control register 0 g0pocr0 0000 x000b 000191h group 0 waveform generation control register 1 g0pocr1 0x00 x000b 000192h group 0 waveform generation control register 2 g0pocr2 0x00 x000b 000193h group 0 waveform generation control register 3 g0pocr3 0x00 x000b 000194h group 0 waveform generation control register 4 g0pocr4 0x00 x000b 000195h group 0 waveform generation control register 5 g0pocr5 0x00 x000b 000196h group 0 waveform generation control register 6 g0pocr6 0x00 x000b 000197h group 0 waveform generation control register 7 g0pocr7 0x00 x000b 000198h group 0 time measurement control register 0 g0tmcr0 00h 000199h group 0 time measurement control register 1 g0tmcr1 00h 00019ah group 0 time measurement control register 2 g0tmcr2 00h 00019bh group 0 time measurement control register 3 g0tmcr3 00h 00019ch group 0 time measurement control register 4 g0tmcr4 00h 00019dh group 0 time measurement control register 5 g0tmcr5 00h 00019eh group 0 time measurement control register 6 g0tmcr6 00h 00019fh group 0 time measurement control register 7 g0tmcr7 00h x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 26 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.8 sfr list (8) address register symbol reset value 0001a0h group 0 base timer register g0bt xxxxh 0001a1h 0001a2h group 0 base timer control register 0 g0bcr0 0000 0000b 0001a3h group 0 base timer control register 1 g0bcr1 0000 0000b 0001a4h group 0 time measurement prescaler register 6 g0tpr6 00h 0001a5h group 0 time measurement prescaler register 7 g0tpr7 00h 0001a6h group 0 function enable register g0fe 00h 0001a7h group 0 function select register g0fs 00h 0001a8h 0001a9h 0001aah 0001abh 0001ach 0001adh 0001aeh 0001afh 0001b0h 0001b1h 0001b2h 0001b3h 0001b4h 0001b5h 0001b6h 0001b7h 0001b8h 0001b9h 0001bah 0001bbh 0001bch 0001bdh 0001beh 0001bfh 0001c0h 0001c1h 0001c2h 0001c3h 0001c4h 0001c5h 0001c6h 0001c7h 0001c8h 0001c9h 0001cah 0001cbh 0001cch 0001cdh 0001ceh 0001cfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 27 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.9 sfr list (9) address register symbol reset value 0001d0h 0001d1h 0001d2h 0001d3h 0001d4h 0001d5h 0001d6h 0001d7h 0001d8h 0001d9h 0001dah 0001dbh 0001dch 0001ddh 0001deh 0001dfh 0001e0h uart3 transmit/receive mode register u3mr 00h 0001e1h uart3 bit rate register u3brg xxh 0001e2h uart3 transmit buffer register u3tb xxxxh 0001e3h 0001e4h uart3 transmit/receive control register 0 u3c0 00x0 1000b 0001e5h uart3 transmit/receive control register 1 u3c1 xxxx 0010b 0001e6h uart3 receive buffer register u3rb xxxxh 0001e7h 0001e8h uart4 transmit/receive mode register u4mr 00h 0001e9h uart4 bit rate register u4brg xxh 0001eah uart4 transmit buffer register u4tb xxxxh 0001ebh 0001ech uart4 transmit/receive control register 0 u4c0 00x0 1000b 0001edh uart4 transmit/receive co ntrol register 1 u4c1 xxxx 0010b 0001eeh uart4 receive buffer register u4rb xxxxh 0001efh 0001f0h uart3, uart4 transmit/receive control register 2 u34con x000 0000b 0001f1h 0001f2h 0001f3h 0001f4h 0001f5h 0001f6h 0001f7h 0001f8h 0001f9h 0001fah 0001fbh 0001fch 0001fdh 0001feh 0001ffh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 28 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.10 sfr list (10) address register symbol reset value 000200h group0 phase shift waveform output mode clock division setting register g0sdr 00h 000201h group0 phase shift waveform output mode control register g0pscr 00h 000202h group1 phase shift waveform output mode clock division setting register g1sdr 00h 000203h group1 phase shift waveform output mode control register g1pscr 00h 000204h 000205h 000206h 000207h 000208h timer b event clock select register tbecks 0000 0000b 000209h 00020ah 00020bh 00020ch 00020dh 00020eh 00020fh 000210h iio0_7 digital debounce register ic07ddr ffh 000211h iio1_7 digital debounce register ic17ddr ffh 000212h 000213h 000214h 000215h 000216h 000217h 000218h 000219h 00021ah 00021bh 00021ch 00021dh 00021eh 00021fh 000220h timer a1 mirror register ta1m xxxxh 000221h 000222h timer a1-1 mirror register ta11m xxxxh 000223h 000224h timer a2 mirror register ta2m xxxxh 000225h 000226h timer a2-1 mirror register ta21m xxxxh 000227h 000228h timer a4 mirror register ta4m xxxxh 000229h 00022ah timer a4-1 mirror register ta41m xxxxh 00022bh 00022ch 00022dh 00022eh 00022fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 29 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.11 sfr list (11) address register symbol reset value 000230h to 0002bfh 0002c0h x0 register/y 0 register x0r/y0r xxxxh 0002c1h 0002c2h x1 register/y 1 register x1r/y1r xxxxh 0002c3h 0002c4h x2 register/y 2 register x2r/y2r xxxxh 0002c5h 0002c6h x3 register/y 3 register x3r/y3r xxxxh 0002c7h 0002c8h x4 register/y 4 register x4r/y4r xxxxh 0002c9h 0002cah x5 register/y 5 register x5r/y5r xxxxh 0002cbh 0002cch x6 register/y6 register x6r/y6r xxxxh 0002cdh 0002ceh x7 register/y 7 register x7r/y7r xxxxh 0002cfh 0002d0h x8 register/y 8 register x8r/y8r xxxxh 0002d1h 0002d2h x9 register/y 9 register x9r/y9r xxxxh 0002d3h 0002d4h x10 register/y10 register x10r/y10r xxxxh 0002d5h 0002d6h x11 register/y11 register x11r/y11r xxxxh 0002d7h 0002d8h x12 register/y12 register x12r/y12r xxxxh 0002d9h 0002dah x13 register/y13 register x13r/y13r xxxxh 0002dbh 0002dch x14 register/y14 register x14r/y14r xxxxh 0002ddh 0002deh x15 register/y15 register x15r/y15r xxxxh 0002dfh 0002e0h x-y control register xyc xxxx xx00b 0002e1h 0002e2h 0002e3h 0002e4h uart1 special mode register 4 u1smr4 00h 0002e5h uart1 special mode register 3 u1smr3 00h 0002e6h uart1 special mode register 2 u1smr2 00h 0002e7h uart1 special mode register u1smr 00h 0002e8h uart1 transmit/receive mode register u1mr 00h 0002e9h uart1 bit rate register u1brg xxh 0002eah uart1 transmit buffer register u1tb xxxxh 0002ebh 0002ech uart1 transmit/receive control register 0 u1c0 0000 1000b 0002edh uart1 transmit/receive control register 1 u1c1 0000 0010b 0002eeh uart1 receive buffer register u1rb xxxxh 0002efh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 30 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.12 sfr list (12) address register symbol reset value 0002f0h 0002f1h 0002f2h 0002f3h 0002f4h 0002f5h 0002f6h 0002f7h 0002f8h 0002f9h 0002fah 0002fbh 0002fch 0002fdh 0002feh 0002ffh 000300h count start register for timers b3, b4, and b5 tbsr 000x xxxxb 000301h 000302h timer a1-1 register ta11 xxxxh 000303h 000304h timer a2-1 register ta21 xxxxh 000305h 000306h timer a4-1 register ta41 xxxxh 000307h 000308h three-phase pwm control register 0 invc0 00h 000309h three-phase pwm control register 1 invc1 00h 00030ah three-phase output buffer register 0 idb0 xx11 1111b 00030bh three-phase output buffer register 1 idb1 xx11 1111b 00030ch dead time timer dtt xxh 00030dh timer b2 interrupt generating frequency set counter ictb2 xxh 00030eh 00030fh 000310h timer b3 register tb3 xxxxh 000311h 000312h timer b4 register tb4 xxxxh 000313h 000314h timer b5 register tb5 xxxxh 000315h 000316h 000317h 000318h 000319h 00031ah 00031bh timer b3 mode register tb3mr 00xx 0000b 00031ch timer b4 mode register tb4mr 00xx 0000b 00031dh timer b5 mode register tb5mr 00xx 0000b 00031eh 00031fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 31 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.13 sfr list (13) address register symbol reset value 000320h 000321h 000322h 000323h 000324h 000325h 000326h 000327h 000328h 000329h 00032ah 00032bh 00032ch 00032dh 00032eh 00032fh 000330h 000331h 000332h 000333h 000334h uart2 special mode register 4 u2smr4 00h 000335h uart2 special mode register 3 u2smr3 00h 000336h uart2 special mode register 2 u2smr2 00h 000337h uart2 special mode register u2smr 00h 000338h uart2 transmit/receive mode register u2mr 00h 000339h uart2 bit rate register u2brg xxh 00033ah uart2 transmit buffer register u2tb xxxxh 00033bh 00033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 00033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 00033eh uart2 receive buffer register u2rb xxxxh 00033fh 000340h count start register tabsr 0000 0000b 000341h clock prescaler reset register cpsrf 0xxx xxxxb 000342h one-shot start register onsf 0000 0000b 000343h trigger select register trgsr 0000 0000b 000344h increment/decrement select register udf 0000 0000b 000345h 000346h timer a0 register ta0 xxxxh 000347h 000348h timer a1 register ta1 xxxxh 000349h 00034ah timer a2 register ta2 xxxxh 00034bh 00034ch timer a3 register ta3 xxxxh 00034dh 00034eh timer a4 register ta4 xxxxh 00034fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 32 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.14 sfr list (14) address register symbol reset value 000350h timer b0 register tb0 xxxxh 000351h 000352h timer b1 register tb1 xxxxh 000353h 000354h timer b2 register tb2 xxxxh 000355h 000356h timer a0 mode register ta0mr 0000 0000b 000357h timer a1 mode register ta1mr 0000 0000b 000358h timer a2 mode register ta2mr 0000 0000b 000359h timer a3 mode register ta3mr 0000 0000b 00035ah timer a4 mode register ta4mr 0000 0000b 00035bh timer b0 mode register tb0mr 00xx 0000b 00035ch timer b1 mode register tb1mr 00xx 0000b 00035dh timer b2 mode register tb2mr 00xx 0000b 00035eh timer b2 special mode register tb2sc xxxx xxx0b 00035fh count source prescaler register tcspr 0000 0000b 000360h 000361h 000362h 000363h 000364h uart0 special mode register 4 u0smr4 00h 000365h uart0 special mode register 3 u0smr3 00h 000366h uart0 special mode register 2 u0smr2 00h 000367h uart0 special mode register u0smr 00h 000368h uart0 transmit/receive mode register u0mr 00h 000369h uart0 bit rate register u0brg xxh 00036ah uart0 transmit buffer register u0tb xxxxh 00036bh 00036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 00036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 00036eh uart0 receive buffer register u0rb xxxxh 00036fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037ah 00037bh 00037ch crc data register crcd xxxxh 00037dh 00037eh crc input register crcin xxh 00037fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 33 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.15 sfr list (15) address register symbol reset value 000380h a/d0 register 0 ad00 00xxh 000381h 000382h a/d0 register 1 ad01 00xxh 000383h 000384h a/d0 register 2 ad02 00xxh 000385h 000386h a/d0 register 3 ad03 00xxh 000387h 000388h a/d0 register 4 ad04 00xxh 000389h 00038ah a/d0 register 5 ad05 00xxh 00038bh 00038ch a/d0 register 6 ad06 00xxh 00038dh 00038eh a/d0 register 7 ad07 00xxh 00038fh 000390h 000391h 000392h a/d0 control register 4 ad0con4 xxxx 00xxb 000393h a/d0 control register 5 ad0con5 00h 000394h a/d0 control register 2 ad0con2 x00x x000b 000395h a/d0 control register 3 ad0con3 xxxx x000b 000396h a/d0 control register 0 ad0con0 00h 000397h a/d0 control register 1 ad0con1 00h 000398h d/a register 0 da0 xxh 000399h 00039ah d/a register 1 da1 xxh 00039bh 00039ch d/a control register dacon xxxx xx00b 00039dh 00039eh 00039fh 0003a0h 0003a1h 0003a2h 0003a3h 0003a4h 0003a5h 0003a6h 0003a7h 0003a8h 0003a9h 0003aah 0003abh 0003ach 0003adh 0003aeh 0003afh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 34 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.16 sfr list (16) address register symbol reset value 0003b0h 0003b1h 0003b2h 0003b3h 0003b4h 0003b5h 0003b6h 0003b7h 0003b8h 0003b9h 0003bah 0003bbh 0003bch 0003bdh 0003beh 0003bfh 0003c0h port p0 register p0 xxh 0003c1h port p1 register p1 xxh 0003c2h port p0 direction register pd0 0000 0000b 0003c3h port p1 direction register pd1 0000 0000b 0003c4h port p2 register p2 xxh 0003c5h port p3 register p3 xxh 0003c6h port p2 direction register pd2 0000 0000b 0003c7h port p3 direction register pd3 0000 0000b 0003c8h port p4 register p4 xxh 0003c9h port p5 register p5 xxh 0003cah port p4 direction register pd4 0000 0000b 0003cbh port p5 direction register pd5 0000 0000b 0003cch port p6 register p6 xxh 0003cdh port p7 register p7 xxh 0003ceh port p6 direction register pd6 0000 0000b 0003cfh port p7 direction register pd7 0000 0000b 0003d0h port p8 register p8 xxh 0003d1h port p9 register p9 xxh 0003d2h port p8 direction register pd8 00x0 0000b 0003d3h port p9 direction register pd9 0000 0x0xb 0003d4h port p10 register p10 xxh 0003d5h 0003d6h port p10 direction register pd10 0000 0000b 0003d7h 0003d8h 0003d9h 0003dah 0003dbh 0003dch 0003ddh 0003deh 0003dfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 35 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.17 sfr list (17) address register symbol reset value 0003e0h 0003e1h 0003e2h 0003e3h 0003e4h 0003e5h 0003e6h 0003e7h 0003e8h 0003e9h 0003eah 0003ebh 0003ech 0003edh 0003eeh 0003efh 0003f0h pull-up control register 0 pur0 0000 0000b 0003f1h pull-up control register 1 pur1 xxxx 0000b 0003f2h pull-up control register 2 pur2 0000 0000b 0003f3h pull-up control register 3 pur3 xxxx xx00b 0003f4h 0003f5h 0003f6h 0003f7h 0003f8h 0003f9h 0003fah 0003fbh 0003fch 0003fdh 0003feh 0003ffh port control register pcr xxxx xxx0b x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 36 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) note: 1. the reset value reflects the value of the protect bit for each block in the flash memory. table 4.18 sfr list (18) address register symbol reset value 040000h flash memory control register 0 fmr0 0x01 xx00b 040001h flash memory status register 0 fmsr0 1000 0000b 040002h 040003h 040004h 040005h 040006h 040007h 040008h flash register protection unlock register 0 fpr0 00h 040009h flash memory control register 1 fmr1 0000 0010b 04000ah block protect bit monitor register 0 fbpm0 ??x? ????b (1) 04000bh block protect bit monitor register 1 fbpm1 xxx? ????b (1) 04000ch 04000dh 04000eh 04000fh 040010h 040011h 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001ah 04001bh 04001ch 04001dh 04001eh 04001fh 040020h pll control register 0 plc0 0000 0001b 040021h pll control register 1 plc1 0001 1111b 040022h 040023h 040024h pll status register pls 1xxx xx00b 040025h 040026h 040027h 040028h 040029h 04002ah 04002bh 04002ch 04002dh 04002eh 04002fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 37 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.19 sfr list (19) address register symbol reset value 040030h to 04003fh 040040h 040041h 040042h 040043h 040044h processor mode register 0 pm0 1000 0000b 040045h 040046h system clock control register 0 cm0 0000 1000b 040047h system clock control register 1 cm1 0010 0000b 040048h processor mode register 3 pm3 00h 040049h 04004ah protect register prcr xxxx x000b 04004bh 04004ch protect register 3 prcr3 0000 0000b 04004dh oscillator stop detection register cm2 00h 04004eh 04004fh 040050h 040051h 040052h 040053h processor mode register 2 pm2 00h 040054h 040055h 040056h 040057h 040058h 040059h 04005ah low speed mode clock control register cm3 xxxx xx00b 04005bh 04005ch 04005dh 04005eh 04005fh 040060h voltage regulator control register vrcr 0000 0000b 040061h 040062h low voltage detector control register lvdc 0000 xx00b 040063h 040064h detection voltage configuration register dvcr 0000 xxxxb 040065h 040066h 040067h 040068h to 040093h x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 38 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.20 sfr list (20) address register symbol reset value 040094h 040095h 040096h 040097h three-phase output buffer control register iobc 0xxx xx0xb 040098h input function select register 0 ifs0 x0x0 x000b 040099h input function select register 1 ifs1 xxxx x0x0b 04009ah input function select register 2 ifs2 0000 0000b 04009bh 04009ch 04009dh input function select register 5 ifs5 xxx0 x0x0b 04009eh input function select register 6 ifs6 xxxx 0000b 04009fh 0400a0h port p0_0 function select register p0_0s 0xxx x000b 0400a1h port p1_0 function select register p1_0s xxxx x000b 0400a2h port p0_1 function select register p0_1s 0xxx x000b 0400a3h port p1_1 function select register p1_1s xxxx x000b 0400a4h port p0_2 function select register p0_2s 0xxx x000b 0400a5h port p1_2 function select register p1_2s xxxx x000b 0400a6h port p0_3 function select register p0_3s 0xxx x000b 0400a7h port p1_3 function select register p1_3s xxxx x000b 0400a8h port p0_4 function select register p0_4s 0xxx x000b 0400a9h port p1_4 function select register p1_4s xxxx x000b 0400aah port p0_5 function sele ct register p0_5s 0xxx x000b 0400abh port p1_5 function se lect register p1_5s xxxx x000b 0400ach port p0_6 function select register p0_6s 0xxx x000b 0400adh port p1_6 function se lect register p1_6s xxxx x000b 0400aeh port p0_7 function sele ct register p0_7s 0xxx x000b 0400afh port p1_7 function se lect register p1_7s xxxx x000b 0400b0h port p2_0 function select register p2_0s 0xxx x000b 0400b1h port p3_0 function select register p3_0s xxxx x000b 0400b2h port p2_1 function select register p2_1s 0xxx x000b 0400b3h port p3_1 function select register p3_1s xxxx x000b 0400b4h port p2_2 function select register p2_2s 0xxx x000b 0400b5h port p3_2 function select register p3_2s xxxx x000b 0400b6h port p2_3 function select register p2_3s 0xxx x000b 0400b7h port p3_3 function select register p3_3s xxxx x000b 0400b8h port p2_4 function select register p2_4s 0xxx x000b 0400b9h port p3_4 function select register p3_4s xxxx x000b 0400bah port p2_5 function sele ct register p2_5s 0xxx x000b 0400bbh port p3_5 function se lect register p3_5s xxxx x000b 0400bch port p2_6 function select register p2_6s 0xxx x000b 0400bdh port p3_6 function se lect register p3_6s xxxx x000b 0400beh port p2_7 function sele ct register p2_7s 0xxx x000b 0400bfh port p3_7 function se lect register p3_7s xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 39 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.21 sfr list (21) address register symbol reset value 0400c0h port p4_0 function se lect register p4_0s xxxx x000b 0400c1h port p5_0 function se lect register p5_0s xxxx x000b 0400c2h port p4_1 function se lect register p4_1s xxxx x000b 0400c3h port p5_1 function se lect register p5_1s xxxx x000b 0400c4h port p4_2 function se lect register p4_2s xxxx x000b 0400c5h port p5_2 function se lect register p5_2s xxxx x000b 0400c6h port p4_3 function se lect register p4_3s xxxx x000b 0400c7h port p5_3 function se lect register p5_3s xxxx x000b 0400c8h port p4_4 function se lect register p4_4s xxxx x000b 0400c9h port p5_4 function se lect register p5_4s xxxx x000b 0400cah port p4_5 function se lect register p4_5s xxxx x000b 0400cbh port p5_5 function se lect register p5_5s xxxx x000b 0400cch port p4_6 function select register p4_6s xxxx x000b 0400cdh port p5_6 function select register p5_6s xxxx x000b 0400ceh port p4_7 function se lect register p4_7s xxxx x000b 0400cfh port p5_7 function se lect register p5_7s xxxx x000b 0400d0h port p6_0 function se lect register p6_0s xxxx x000b 0400d1h port p7_0 function se lect register p7_0s xxxx x000b 0400d2h port p6_1 function se lect register p6_1s xxxx x000b 0400d3h port p7_1 function se lect register p7_1s xxxx x000b 0400d4h port p6_2 function se lect register p6_2s xxxx x000b 0400d5h port p7_2 function se lect register p7_2s xxxx x000b 0400d6h port p6_3 function se lect register p6_3s xxxx x000b 0400d7h port p7_3 function se lect register p7_3s xxxx x000b 0400d8h port p6_4 function se lect register p6_4s xxxx x000b 0400d9h port p7_4 function se lect register p7_4s xxxx x000b 0400dah port p6_5 function se lect register p6_5s xxxx x000b 0400dbh port p7_5 function se lect register p7_5s xxxx x000b 0400dch port p6_6 function select register p6_6s xxxx x000b 0400ddh port p7_6 function select register p7_6s xxxx x000b 0400deh port p6_7 function se lect register p6_7s xxxx x000b 0400dfh port p7_7 function se lect register p7_7s xxxx x000b 0400e0h port p8_0 function select register p8_0s xxxx x000b 0400e1h 0400e2h port p8_1 function select register p8_1s xxxx x000b 0400e3h 0400e4h port p8_2 function select register p8_2s xxxx x000b 0400e5h 0400e6h port p8_3 function select register p8_3s xxxx x000b 0400e7h port p9_3 function select register p9_3s 0xxx x000b 0400e8h port p8_4 function select register p8_4s xxxx x000b 0400e9h port p9_4 function select register p9_4s 0xxx x000b 0400eah 0400ebh port p9_5 function se lect register p9_5s 0xxx x000b 0400ech port p8_6 function se lect register p8_6s xxxx x000b 0400edh port p9_6 function se lect register p9_6s 0xxx x000b 0400eeh port p8_7 function se lect register p8_7s xxxx x000b 0400efh port p9_7 function se lect register p9_7s xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 40 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.22 sfr list (22) address register symbol reset value 0400f0h port p10_0 function select register p10_0s 0xxx x000b 0400f1h 0400f2h port p10_1 function select register p10_1s 0xxx x000b 0400f3h 0400f4h port p10_2 function select register p10_2s 0xxx x000b 0400f5h 0400f6h port p10_3 function select register p10_3s 0xxx x000b 0400f7h 0400f8h port p10_4 function select register p10_4s 0xxx x000b 0400f9h 0400fah port p10_5 function select register p10_5s 0xxx x000b 0400fbh 0400fch port p10_6 function select register p10_6s 0xxx x000b 0400fdh 0400feh port p10_7 function select register p10_7s 0xxx x000b 0400ffh 040100h 040101h 040102h 040103h 040104h 040105h 040106h 040107h 040108h 040109h 04010ah 04010bh 04010ch 04010dh 04010eh 04010fh 040110h 040111h 040112h 040113h 040114h 040115h 040116h 040117h 040118h 040119h 04011ah 04011bh 04011ch 04011dh 04011eh 04011fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 41 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.23 sfr list (23) address register symbol reset value 040120h to 04403fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404ah 04404bh 04404ch protect register 4 prcr4 0000 0000b 04404dh watchdog timer clock control register wdk 0000 0000b 04404eh watchdog timer start register wdts xxxx xxxxb 04404fh watchdog timer control register wdc 000x xxxxb 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405ah 04405bh 04405ch 04405dh 04405eh 04405fh protect register 2 prcr2 0xxx xxxxb x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 42 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.24 sfr list (24) address register symbol reset value 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406ah 04406bh 04406ch 04406dh 04406eh 04406fh external interrupt request source select register 0 ifsr0 0000 0000b 044070h dma0 request source select register 2 dm0sl2 xx00 0000b 044071h dma1 request source select register 2 dm1sl2 xx00 0000b 044072h dma2 request source select register 2 dm2sl2 xx00 0000b 044073h dma3 request source select register 2 dm3sl2 xx00 0000b 044074h 044075h 044076h 044077h 044078h dma0 request source select register dm0sl xxx0 0000b 044079h dma1 request source select register dm1sl xxx0 0000b 04407ah dma2 request source select register dm2sl xxx0 0000b 04407bh dma3 request source select register dm3sl xxx0 0000b 04407ch 04407dh wake-up ipl setting register 2 ripl2 xx0x 0000b 04407eh 04407fh wake-up ipl setting register 1 ripl1 xx0x 0000b 044080h external interrupt input filter select register 0 intf0 0000 0000b 044081h 044082h external interrupt input filter select register 1 intf1 0000 0000b 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408ah 04408bh 04408ch 04408dh 04408eh 04408fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 43 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.25 sfr list (25) address register symbol reset value 044090h to 044dffh 044e00h lin channel window select/input signal low detection status register lcw 0000 0000b 044e01h lin baud rate generator control register lbrg 0000 0000b 044e02h lin baud rate prescaler 0 lbrp0 00h 044e03h lin baud rate prescaler 1 lbrp1 00h 044e04h lin mode register 0 lmd0 0000 0000b 044e05h lin mode register 1 lmd1 00h 044e06h lin wake-up setting register lwup 00h 044e07h 044e08h lin break field setting register lbrk 0000 0000b 044e09h lin space setting register lspc 0000 0000b 044e0ah lin response field setting register lrfc 0000 0000b 044e0bh lin id buffer register lidb 00h 044e0ch lin status control register lsc 0000 0000b 044e0dh lin transmission control register ltc 0000 0000b 044e0eh lin status register lst 0000 0000b 044e0fh lin error status register lest 0000 0000b 044e10h lin data 1 buffer register ldb1 00h 044e11h lin data 2 buffer register ldb2 00h 044e12h lin data 3 buffer register ldb3 00h 044e13h lin data 4 buffer register ldb4 00h 044e14h lin data 5 buffer register ldb5 00h 044e15h lin data 6 buffer register ldb6 00h 044e16h lin data 7 buffer register ldb7 00h 044e17h lin data 8 buffer register ldb8 00h 044e18h 044e19h 044e1ah 044e1bh 044e1ch 044e1dh 044e1eh 044e1fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 44 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.26 sfr list (26) address register symbol reset value 044e20h to 044effh 044f00h 044f01h 044f02h 044f03h 044f04h 044f05h 044f06h ss0 receive data register ss0rdr ffh 044f07h ss0 receive data register (h) ss0rdr (h) ffh 044f08h ss0 control register h ss0crh 00h 044f09h ss0 control register l ss0crl 0111 1101b 044f0ah ss0 mode register ss0mr 0001 0000b 044f0bh ss0 enable register ss0er 00h 044f0ch ss0 status register ss0sr 00h 044f0dh ss0 mode register 2 ss0mr2 00h 044f0eh ss0 transmit data register ss0tdr ffh 044f0fh ss0 transmit data register (h) ss0tdr (h) ffh 044f10h 044f11h 044f12h 044f13h 044f14h 044f15h 044f16h ss1 receive data register ss1rdr ffh 044f17h ss1 receive data register (h) ss1rdr (h) ffh 044f18h ss1 control register h ss1crh 00h 044f19h ss1 control register l ss1crl 0111 1101b 044f1ah ss1 mode register ss1mr 0001 0000b 044f1bh ss1 enable register ss1er 00h 044f1ch ss1 status register ss1sr 00h 044f1dh ss1 mode register 2 ss1mr2 00h 044f1eh ss1 transmit data register ss1tdr ffh 044f1fh ss1 transmit data register (h) ss1tdr (h) ffh 044f20h 044f21h 044f22h 044f23h 044f24h 044f25h 044f26h ss2 receive data register ss2rdr ffh 044f27h ss2 receive data register (h) ss2rdr (h) ffh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 45 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.27 sfr list (27) address register symbol reset value 044f28h ss2 control register h ss2crh 00h 044f29h ss2 control register l ss2crl 0111 1101b 044f2ah ss2 mode register ss2mr 0001 0000b 044f2bh ss2 enable register ss2er 00h 044f2ch ss2 status register ss2sr 00h 044f2dh ss2 mode register 2 ss2mr2 00h 044f2eh ss2 transmit data register ss2tdr ffh 044f2fh ss2 transmit data register (h) ss2tdr (h) ffh 044f30h 044f31h 044f32h 044f33h 044f34h 044f35h 044f36h 044f37h 044f38h 044f39h 044f3ah 044f3bh 044f3ch 044f3dh 044f3eh 044f3fh 044f40h 044f41h 044f42h 044f43h 044f44h 044f45h 044f46h 044f47h 044f48h 044f49h 044f4ah 044f4bh 044f4ch 044f4dh 044f4eh 044f4fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 46 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.28 sfr list (28) address register symbol reset value 044f50h to 044fdfh 044fe0h e 2 dataflash address register e2fa xxxx 0000h 044fe1h 044fe2h 044fe3h 044fe4h 044fe5h 044fe6h 044fe7h 044fe8h e 2 dataflash instruction register e2fi xx00h 044fe9h 044feah 044febh 044fech e 2 dataflash data register e2fd xxxxh 044fedh 044feeh 044fefh 044ff0h e 2 dataflash mode register e2fm 0000 0000b 044ff1h 044ff2h e 2 dataflash control register e2fc xxxx xxx0b 044ff3h 044ff4h e 2 dataflash status register 1 e2fs1 xxxx xxx0b 044ff5h 044ff6h 044ff7h 044ff8h 044ff9h 044ffah 044ffbh 044ffch 044ffdh 044ffeh 044fffh 045000h 045001h e 2 dataflash status register 0 e2fs0 xxxx xxxxb 045002h 045003h 045004h 045005h 045006h 045007h 045008h to 045fffh 046000h to 0467ffh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 47 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.29 sfr list (29) address register symbol reset value 046800h to 0477ffh 047800h can1 mailbox 0: message identifier c1mb0 xxxx xxxxh 047801h 047802h 047803h 047804h 047805h can1 mailbox 0: data length xxh 047806h can1 mailbox 0: data field xxxx xxxx xxxx xxxxh 047807h 047808h 047809h 04780ah 04780bh 04780ch 04780dh 04780eh can1 mailbox 0: time stamp xxxxh 04780fh 047810h can1 mailbox 1: message identifier c1mb1 xxxx xxxxh 047811h 047812h 047813h 047814h 047815h can1 mailbox 1: data length xxh 047816h can1 mailbox 1: data field xxxx xxxx xxxx xxxxh 047817h 047818h 047819h 04781ah 04781bh 04781ch 04781dh 04781eh can1 mailbox 1: time stamp xxxxh 04781fh 047820h can1 mailbox 2: message identifier c1mb2 xxxx xxxxh 047821h 047822h 047823h 047824h 047825h can1 mailbox 2: data length xxh 047826h can1 mailbox 2: data field xxxx xxxx xxxx xxxxh 047827h 047828h 047829h 04782ah 04782bh 04782ch 04782dh 04782eh can1 mailbox 2: time stamp xxxxh 04782fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 48 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.30 sfr list (30) address register symbol reset value 047830h can1 mailbox 3: message identifier c1mb3 xxxx xxxxh 047831h 047832h 047833h 047834h 047835h can1 mailbox 3: data length xxh 047836h can1 mailbox 3: data field xxxx xxxx xxxx xxxxh 047837h 047838h 047839h 04783ah 04783bh 04783ch 04783dh 04783eh can1 mailbox 3: time stamp xxxxh 04783fh 047840h can1 mailbox 4: message identifier c1mb4 xxxx xxxxh 047841h 047842h 047843h 047844h 047845h can1 mailbox 4: data length xxh 047846h can1 mailbox 4: data field xxxx xxxx xxxx xxxxh 047847h 047848h 047849h 04784ah 04784bh 04784ch 04784dh 04784eh can1 mailbox 4: time stamp xxxxh 04784fh 047850h can1 mailbox 5: message identifier c1mb5 xxxx xxxxh 047851h 047852h 047853h 047854h 047855h can1 mailbox 5: data length xxh 047856h can1 mailbox 5: data field xxxx xxxx xxxx xxxxh 047857h 047858h 047859h 04785ah 04785bh 04785ch 04785dh 04785eh can1 mailbox 5: time stamp xxxxh 04785fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 49 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.31 sfr list (31) address register symbol reset value 047860h can1 mailbox 6: message identifier c1mb6 xxxx xxxxh 047861h 047862h 047863h 047864h 047865h can1 mailbox 6: data length xxh 047866h can1 mailbox 6: data field xxxx xxxx xxxx xxxxh 047867h 047868h 047869h 04786ah 04786bh 04786ch 04786dh 04786eh can1 mailbox 6: time stamp xxxxh 04786fh 047870h can1 mailbox 7: message identifier c1mb7 xxxx xxxxh 047871h 047872h 047873h 047874h 047875h can1 mailbox 7: data length xxh 047876h can1 mailbox 7: data field xxxx xxxx xxxx xxxxh 047877h 047878h 047879h 04787ah 04787bh 04787ch 04787dh 04787eh can1 mailbox 7: time stamp xxxxh 04787fh 047880h can1 mailbox 8: message identifier c1mb8 xxxx xxxxh 047881h 047882h 047883h 047884h 047885h can1 mailbox 8: data length xxh 047886h can1 mailbox 8: data field xxxx xxxx xxxx xxxxh 047887h 047888h 047889h 04788ah 04788bh 04788ch 04788dh 04788eh can1 mailbox 8: time stamp xxxxh 04788fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 50 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.32 sfr list (32) address register symbol reset value 047890h can1 mailbox 9: message identifier c1mb9 xxxx xxxxh 047891h 047892h 047893h 047894h 047895h can1 mailbox 9: data length xxh 047896h can1 mailbox 9: data field xxxx xxxx xxxx xxxxh 047897h 047898h 047899h 04789ah 04789bh 04789ch 04789dh 04789eh can1 mailbox 9: time stamp xxxxh 04789fh 0478a0h can1 mailbox 10: message identifier c1mb10 xxxx xxxxh 0478a1h 0478a2h 0478a3h 0478a4h 0478a5h can1 mailbox 10: data length xxh 0478a6h can1 mailbox 10: data field xxxx xxxx xxxx xxxxh 0478a7h 0478a8h 0478a9h 0478aah 0478abh 0478ach 0478adh 0478aeh can1 mailbox 10: time stamp xxxxh 0478afh 0478b0h can1 mailbox 11: message identifier c1mb11 xxxx xxxxh 0478b1h 0478b2h 0478b3h 0478b4h 0478b5h can1 mailbox 11: data length xxh 0478b6h can1 mailbox 11: data field xxxx xxxx xxxx xxxxh 0478b7h 0478b8h 0478b9h 0478bah 0478bbh 0478bch 0478bdh 0478beh can1 mailbox 11: time stamp xxxxh 0478bfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 51 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.33 sfr list (33) address register symbol reset value 0478c0h can1 mailbox 12: message identifier c1mb12 xxxx xxxxh 0478c1h 0478c2h 0478c3h 0478c4h 0478c5h can1 mailbox 12: data length xxh 0478c6h can1 mailbox 12: data field xxxx xxxx xxxx xxxxh 0478c7h 0478c8h 0478c9h 0478cah 0478cbh 0478cch 0478cdh 0478ceh can1 mailbox 12: time stamp xxxxh 0478cfh 0478d0h can1 mailbox 13: message identifier c1mb13 xxxx xxxxh 0478d1h 0478d2h 0478d3h 0478d4h 0478d5h can1 mailbox 13: data length xxh 0478d6h can1 mailbox 13: data field xxxx xxxx xxxx xxxxh 0478d7h 0478d8h 0478d9h 0478dah 0478dbh 0478dch 0478ddh 0478deh can1 mailbox 13: time stamp xxxxh 0478dfh 0478e0h can1 mailbox 14: message identifier c1mb14 xxxx xxxxh 0478e1h 0478e2h 0478e3h 0478e4h 0478e5h can1 mailbox 14: data length xxh 0478e6h can1 mailbox 14: data field xxxx xxxx xxxx xxxxh 0478e7h 0478e8h 0478e9h 0478eah 0478ebh 0478ech 0478edh 0478eeh can1 mailbox 14: time stamp xxxxh 0478efh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 52 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.34 sfr list (34) address register symbol reset value 0478f0h can1 mailbox 15: mess age identifier c1mb15 xxxx xxxxh 0478f1h 0478f2h 0478f3h 0478f4h 0478f5h can1 mailbox 15: data length xxh 0478f6h can1 mailbox 15: data field xxxx xxxx xxxx xxxxh 0478f7h 0478f8h 0478f9h 0478fah 0478fbh 0478fch 0478fdh 0478feh can1 mailbox 15: time stamp xxxxh 0478ffh 047900h can1 mailbox 16: message identifier c1mb16 xxxx xxxxh 047901h 047902h 047903h 047904h 047905h can1 mailbox 16: data length xxh 047906h can1 mailbox 16: data field xxxx xxxx xxxx xxxxh 047907h 047908h 047909h 04790ah 04790bh 04790ch 04790dh 04790eh can1 mailbox 16: time stamp xxxxh 04790fh 047910h can1 mailbox 17: message identifier c1mb17 xxxx xxxxh 047911h 047912h 047913h 047914h 047915h can1 mailbox 17: data length xxh 047916h can1 mailbox 17: data field xxxx xxxx xxxx xxxxh 047917h 047918h 047919h 04791ah 04791bh 04791ch 04791dh 04791eh can1 mailbox 17: time stamp xxxxh 04791fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 53 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.35 sfr list (35) address register symbol reset value 047920h can1 mailbox 18: message identifier c1mb18 xxxx xxxxh 047921h 047922h 047923h 047924h 047925h can1 mailbox 18: data length xxh 047926h can1 mailbox 18: data field xxxx xxxx xxxx xxxxh 047927h 047928h 047929h 04792ah 04792bh 04792ch 04792dh 04792eh can1 mailbox18: time stamp xxxxh 04792fh 047930h can1 mailbox 19: message identifier c1mb19 xxxx xxxxh 047931h 047932h 047933h 047934h 047935h can1 mailbox 19: data length xxh 047936h can1 mailbox 19: data field xxxx xxxx xxxx xxxxh 047937h 047938h 047939h 04793ah 04793bh 04793ch 04793dh 04793eh can1 mailbox 19: time stamp xxxxh 04793fh 047940h can1 mailbox 20: message identifier c1mb20 xxxx xxxxh 047941h 047942h 047943h 047944h 047945h can1 mailbox 20: data length xxh 047946h can1 mailbox 20: data field xxxx xxxx xxxx xxxxh 047947h 047948h 047949h 04794ah 04794bh 04794ch 04794dh 04794eh can1 mailbox 20: time stamp xxxxh 04794fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 54 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.36 sfr list (36) address register symbol reset value 047950h can1 mailbox 21: message identifier c1mb21 xxxx xxxxh 047951h 047952h 047953h 047954h 047955h can1 mailbox 21: data length xxh 047956h can1 mailbox 21: data field xxxx xxxx xxxx xxxxh 047957h 047958h 047959h 04795ah 04795bh 04795ch 04795dh 04795eh can1 mailbox 21: time stamp xxxxh 04795fh 047960h can1 mailbox 22: identifier c1mb22 xxxx xxxxh 047961h 047962h 047963h 047964h 047965h can1 mailbox 22: data length xxh 047966h can1 mailbox 22: data field xxxx xxxx xxxx xxxxh 047967h 047968h 047969h 04796ah 04796bh 04796ch 04796dh 04796eh can1 mailbox 22: time stamp xxxxh 04796fh 047970h can1 mailbox 23: message identifier c1mb23 xxxx xxxxh 047971h 047972h 047973h 047974h 047975h can1 mailbox 23: data length xxh 047976h can1 mailbox 23: data field xxxx xxxx xxxx xxxxh 047977h 047978h 047979h 04797ah 04797bh 04797ch 04797dh 04797eh can1 mailbox 23: time stamp xxxxh 04797fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 55 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.37 sfr list (37) address register symbol reset value 047980h can1 mailbox 24: message identifier c1mb24 xxxx xxxxh 047981h 047982h 047983h 047984h 047985h can1 mailbox 24: data length xxh 047986h can1 mailbox 24: data field xxxx xxxx xxxx xxxxh 047987h 047988h 047989h 04798ah 04798bh 04798ch 04798dh 04798eh can1 mailbox 24: time stamp xxxxh 04798fh 047990h can1 mailbox 25: message identifier c1mb25 xxxx xxxxh 047991h 047992h 047993h 047994h 047995h can1 mailbox 25: data length xxh 047996h can1 mailbox 25: data field xxxx xxxx xxxx xxxxh 047997h 047998h 047999h 04799ah 04799bh 04799ch 04799dh 04799eh can1 mailbox 25: time stamp xxxxh 04799fh 0479a0h can1 mailbox 26: message identifier c1mb26 xxxx xxxxh 0479a1h 0479a2h 0479a3h 0479a4h 0479a5h can1 mailbox 26: data length xxh 0479a6h can1 mailbox 26: data field xxxx xxxx xxxx xxxxh 0479a7h 0479a8h 0479a9h 0479aah 0479abh 0479ach 0479adh 0479aeh can1 mailbox 26: time stamp xxxxh 0479afh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 56 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.38 sfr list (38) address register symbol reset value 0479b0h can1 mailbox 27: message identifier c1mb27 xxxx xxxxh 0479b1h 0479b2h 0479b3h 0479b4h 0479b5h can1 mailbox 27: data length xxh 0479b6h can1 mailbox 27: data field xxxx xxxx xxxx xxxxh 0479b7h 0479b8h 0479b9h 0479bah 0479bbh 0479bch 0479bdh 0479beh can1 mailbox 27: time stamp xxxxh 0479bfh 0479c0h can1 mailbox 28: message identifier c1mb28 xxxx xxxxh 0479c1h 0479c2h 0479c3h 0479c4h 0479c5h can1 mailbox 28: data length xxh 0479c6h can1 mailbox 28: data field xxxx xxxx xxxx xxxxh 0479c7h 0479c8h 0479c9h 0479cah 0479cbh 0479cch 0479cdh 0479ceh can1 mailbox 28: time stamp xxxxh 0479cfh 0479d0h can1 mailbox 29: message identifier c1mb29 xxxx xxxxh 0479d1h 0479d2h 0479d3h 0479d4h 0479d5h can1 mailbox 29: data length xxh 0479d6h can1 mailbox 29: data field xxxx xxxx xxxx xxxxh 0479d7h 0479d8h 0479d9h 0479dah 0479dbh 0479dch 0479ddh 0479deh can1 mailbox 29: time stamp xxxxh 0479dfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 57 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.39 sfr list (39) address register symbol reset value 0479e0h can1 mailbox 30: message identifier c1mb30 xxxx xxxxh 0479e1h 0479e2h 0479e3h 0479e4h 0479e5h can1 mailbox 30: data length xxh 0479e6h can1 mailbox 30: data field xxxx xxxx xxxx xxxxh 0479e7h 0479e8h 0479e9h 0479eah 0479ebh 0479ech 0479edh 0479eeh can1 mailbox 30: time stamp xxxxh 0479efh 0479f0h can1 mailbox 31: mess age identifier c1mb31 xxxx xxxxh 0479f1h 0479f2h 0479f3h 0479f4h 0479f5h can1 mailbox 31: data length xxh 0479f6h can1 mailbox 31: data field xxxx xxxx xxxx xxxxh 0479f7h 0479f8h 0479f9h 0479fah 0479fbh 0479fch 0479fdh 0479feh can1 mailbox 31: time stamp xxxxh 0479ffh 047a00h can1 mask register 0 c1mkr0 xxxx xxxxh 047a01h 047a02h 047a03h 047a04h can1 mask register 1 c1mkr1 xxxx xxxxh 047a05h 047a06h 047a07h 047a08h can1 mask register 2 c1mkr2 xxxx xxxxh 047a09h 047a0ah 047a0bh 047a0ch can1 mask register 3 c1mkr3 xxxx xxxxh 047a0dh 047a0eh 047a0fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 58 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.40 sfr list (40) address register symbol reset value 047a10h can1 mask register 4 c1mkr4 xxxx xxxxh 047a11h 047a12h 047a13h 047a14h can1 mask register 5 c1mkr5 xxxx xxxxh 047a15h 047a16h 047a17h 047a18h can1 mask register 6 c1mkr6 xxxx xxxxh 047a19h 047a1ah 047a1bh 047a1ch can1 mask register 7 c1mkr7 xxxx xxxxh 047a1dh 047a1eh 047a1fh 047a20h can1 fifo received id compare register 0 c1fidcr0 xxxx xxxxh 047a21h 047a22h 047a23h 047a24h can1 fifo received id compare register 1 c1fidcr1 xxxx xxxxh 047a25h 047a26h 047a27h 047a28h can1 mask invalid register c1mkivlr xxxx xxxxh 047a29h 047a2ah 047a2bh 047a2ch can1 mailbox interrupt enable register c1mier xxxx xxxxh 047a2dh 047a2eh 047a2fh 047a30h 047a31h 047a32h 047a33h 047a34h 047a35h 047a36h 047a37h 047a38h 047a39h 047a3ah 047a3bh 047a3ch 047a3dh 047a3eh 047a3fh 047a40h to 047b1fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 59 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.41 sfr list (41) address register symbol reset value 047b20h can1 message control register 0 c1mctl0 00h 047b21h can1 message control register 1 c1mctl1 00h 047b22h can1 message control register 2 c1mctl2 00h 047b23h can1 message control register 3 c1mctl3 00h 047b24h can1 message control register 4 c1mctl4 00h 047b25h can1 message control register 5 c1mctl5 00h 047b26h can1 message control register 6 c1mctl6 00h 047b27h can1 message control register 7 c1mctl7 00h 047b28h can1 message control register 8 c1mctl8 00h 047b29h can1 message control register 9 c1mctl9 00h 047b2ah can1 message control register 10 c1mctl10 00h 047b2bh can1 message control register 11 c1mctl11 00h 047b2ch can1 message control register 12 c1mctl12 00h 047b2dh can1 message control register 13 c1mctl13 00h 047b2eh can1 message control register 14 c1mctl14 00h 047b2fh can1 message control register 15 c1mctl15 00h 047b30h can1 message control register 16 c1mctl16 00h 047b31h can1 message control register 17 c1mctl17 00h 047b32h can1 message control register 18 c1mctl18 00h 047b33h can1 message control register 19 c1mctl19 00h 047b34h can1 message control register 20 c1mctl20 00h 047b35h can1 message control register 21 c1mctl21 00h 047b36h can1 message control register 22 c1mctl22 00h 047b37h can1 message control register 23 c1mctl23 00h 047b38h can1 message control register 24 c1mctl24 00h 047b39h can1 message control register 25 c1mctl25 00h 047b3ah can1 message control register 26 c1mctl26 00h 047b3bh can1 message control register 27 c1mctl27 00h 047b3ch can1 message control register 28 c1mctl28 00h 047b3dh can1 message control register 29 c1mctl29 00h 047b3eh can1 message control register 30 c1mctl30 00h 047b3fh can1 message control register 31 c1mctl31 00h x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 60 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.42 sfr list (42) address register symbol reset value 047b40h can1 control register c1ctlr 0000 0101b 047b41h 0000 0000b 047b42h can1 status register c1str 0000 0101b 047b43h 0000 0000b 047b44h can1 bit configuration register c1bcr 00 0000h 047b45h 047b46h 047b47h can1 clock select register c1clkr 000x 0000b 047b48h can1 receive fifo cont rol register c1rfcr 1000 0000b 047b49h can1 receive fifo pointer control register c1rfpcr xxh 047b4ah can1 transmit fifo c ontrol register c1tfcr 1000 0000b 047b4bh can1 transmit fifo pointer control register c1tfpcr xxh 047b4ch can1 error interrupt enable register c1eier 00h 047b4dh can1 error interrupt factor judge register c1eifr 00h 047b4eh can1 receive error count register c1recr 00h 047b4fh can1 transmit error count register c1tecr 00h 047b50h can1 error code store register c1ecsr 00h 047b51h can1 channel search support register c1cssr xxh 047b52h can1 mailbox search status register c1mssr 1000 0000b 047b53h can1 mailbox search mode register c1msmr 0000 0000b 047b54h can1 time stamp register c1tsr 0000h 047b55h 047b56h can1 acceptance filter support register c1afsr xxxxh 047b57h 047b58h can1 test control register c1tcr 00h 047b59h 047b5ah 047b5bh 047b5ch 047b5dh 047b5eh 047b5fh 047b60h to 047bffh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 61 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.43 sfr list (43) address register symbol reset value 047c00h can0 mailbox 0: me ssage identifier c0mb0 xxxx xxxxh 047c01h 047c02h 047c03h 047c04h 047c05h can0 mailbox 0: data length xxh 047c06h can0 mailbox 0: data field xxxx xxxx xxxx xxxxh 047c07h 047c08h 047c09h 047c0ah 047c0bh 047c0ch 047c0dh 047c0eh can0 mailbox 0: time stamp xxxxh 047c0fh 047c10h can0 mailbox 1: me ssage identifier c0mb1 xxxx xxxxh 047c11h 047c12h 047c13h 047c14h 047c15h can0 mailbox 1: data length xxh 047c16h can0 mailbox 1: data field xxxx xxxx xxxx xxxxh 047c17h 047c18h 047c19h 047c1ah 047c1bh 047c1ch 047c1dh 047c1eh can0 mailbox 1: time stamp xxxxh 047c1fh 047c20h can0 mailbox 2: me ssage identifier c0mb2 xxxx xxxxh 047c21h 047c22h 047c23h 047c24h 047c25h can0 mailbox 2: data length xxh 047c26h can0 mailbox 2: data field xxxx xxxx xxxx xxxxh 047c27h 047c28h 047c29h 047c2ah 047c2bh 047c2ch 047c2dh 047c2eh can0 mailbox 2: time stamp xxxxh 047c2fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 62 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.44 sfr list (44) address register symbol reset value 047c30h can0 mailbox 3: me ssage identifier c0mb3 xxxx xxxxh 047c31h 047c32h 047c33h 047c34h 047c35h can0 mailbox 3: data length xxh 047c36h can0 mailbox 3: data field xxxx xxxx xxxx xxxxh 047c37h 047c38h 047c39h 047c3ah 047c3bh 047c3ch 047c3dh 047c3eh can0 mailbox 3: time stamp xxxxh 047c3fh 047c40h can0 mailbox 4: me ssage identifier c0mb4 xxxx xxxxh 047c41h 047c42h 047c43h 047c44h 047c45h can0 mailbox 4: data length xxh 047c46h can0 mailbox 4: data field xxxx xxxx xxxx xxxxh 047c47h 047c48h 047c49h 047c4ah 047c4bh 047c4ch 047c4dh 047c4eh can0 mailbox 4: time stamp xxxxh 047c4fh 047c50h can0 mailbox 5: me ssage identifier c0mb5 xxxx xxxxh 047c51h 047c52h 047c53h 047c54h 047c55h can0 mailbox 5: data length xxh 047c56h can0 mailbox 5: data field xxxx xxxx xxxx xxxxh 047c57h 047c58h 047c59h 047c5ah 047c5bh 047c5ch 047c5dh 047c5eh can0 mailbox 5: time stamp xxxxh 047c5fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 63 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.45 sfr list (45) address register symbol reset value 047c60h can0 mailbox 6: me ssage identifier c0mb6 xxxx xxxxh 047c61h 047c62h 047c63h 047c64h 047c65h can0 mailbox 6: data length xxh 047c66h can0 mailbox 6: data field xxxx xxxx xxxx xxxxh 047c67h 047c68h 047c69h 047c6ah 047c6bh 047c6ch 047c6dh 047c6eh can0 mailbox 6: time stamp xxxxh 047c6fh 047c70h can0 mailbox 7: me ssage identifier c0mb7 xxxx xxxxh 047c71h 047c72h 047c73h 047c74h 047c75h can0 mailbox 7: data length xxh 047c76h can0 mailbox 7: data field xxxx xxxx xxxx xxxxh 047c77h 047c78h 047c79h 047c7ah 047c7bh 047c7ch 047c7dh 047c7eh can0 mailbox 7: time stamp xxxxh 047c7fh 047c80h can0 mailbox 8: me ssage identifier c0mb8 xxxx xxxxh 047c81h 047c82h 047c83h 047c84h 047c85h can0 mailbox 8: data length xxh 047c86h can0 mailbox 8: data field xxxx xxxx xxxx xxxxh 047c87h 047c88h 047c89h 047c8ah 047c8bh 047c8ch 047c8dh 047c8eh can0 mailbox 8: time stamp xxxxh 047c8fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 64 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.46 sfr list (46) address register symbol reset value 047c90h can0 mailbox 9: me ssage identifier c0mb9 xxxx xxxxh 047c91h 047c92h 047c93h 047c94h 047c95h can0 mailbox 9: data length xxh 047c96h can0 mailbox 9: data field xxxx xxxx xxxx xxxxh 047c97h 047c98h 047c99h 047c9ah 047c9bh 047c9ch 047c9dh 047c9eh can0 mailbox 9: time stamp xxxxh 047c9fh 047ca0h can0 mailbox 10: message identifier c0mb10 xxxx xxxxh 047ca1h 047ca2h 047ca3h 047ca4h 047ca5h can0 mailbox 10: data length xxh 047ca6h can0 mailbox 10: data field xxxx xxxx xxxx xxxxh 047ca7h 047ca8h 047ca9h 047caah 047cabh 047cach 047cadh 047caeh can0 mailbox 10: time stamp xxxxh 047cafh 047cb0h can0 mailbox 11: message identifier c0mb11 xxxx xxxxh 047cb1h 047cb2h 047cb3h 047cb4h 047cb5h can0 mailbox 11: data length xxh 047cb6h can0 mailbox 11: data field xxxx xxxx xxxx xxxxh 047cb7h 047cb8h 047cb9h 047cbah 047cbbh 047cbch 047cbdh 047cbeh can0 mailbox 11: time stamp xxxxh 047cbfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 65 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.47 sfr list (47) address register symbol reset value 047cc0h can0 mailbox 12: message identifier c0mb12 xxxx xxxxh 047cc1h 047cc2h 047cc3h 047cc4h 047cc5h can0 mailbox 12: data length xxh 047cc6h can0 mailbox 12: data field xxxx xxxx xxxx xxxxh 047cc7h 047cc8h 047cc9h 047ccah 047ccbh 047ccch 047ccdh 047cceh can0 mailbox 12: time stamp xxxxh 047ccfh 047cd0h can0 mailbox 13: message identifier c0mb13 xxxx xxxxh 047cd1h 047cd2h 047cd3h 047cd4h 047cd5h can0 mailbox 13: data length xxh 047cd6h can0 mailbox 13: data field xxxx xxxx xxxx xxxxh 047cd7h 047cd8h 047cd9h 047cdah 047cdbh 047cdch 047cddh 047cdeh can0 mailbox 13: time stamp xxxxh 047cdfh 047ce0h can0 mailbox 14: message identifier c0mb14 xxxx xxxxh 047ce1h 047ce2h 047ce3h 047ce4h 047ce5h can0 mailbox 14: data length xxh 047ce6h can0 mailbox 14: data field xxxx xxxx xxxx xxxxh 047ce7h 047ce8h 047ce9h 047ceah 047cebh 047cech 047cedh 047ceeh can0 mailbox 14: time stamp xxxxh 047cefh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 66 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.48 sfr list (48) address register symbol reset value 047cf0h can0 mailbox 15: message identifier c0mb15 xxxx xxxxh 047cf1h 047cf2h 047cf3h 047cf4h 047cf5h can0 mailbox 15: data length xxh 047cf6h can0 mailbox 15: data field xxxx xxxx xxxx xxxxh 047cf7h 047cf8h 047cf9h 047cfah 047cfbh 047cfch 047cfdh 047cfeh can0 mailbox 15: time stamp xxxxh 047cffh 047d00h can0 mailbox 16: message identifier c0mb16 xxxx xxxxh 047d01h 047d02h 047d03h 047d04h 047d05h can0 mailbox 16: data length xxh 047d06h can0 mailbox 16: data field xxxx xxxx xxxx xxxxh 047d07h 047d08h 047d09h 047d0ah 047d0bh 047d0ch 047d0dh 047d0eh can0 mailbox 16: time stamp xxxxh 047d0fh 047d10h can0 mailbox 17: message identifier c0mb17 xxxx xxxxh 047d11h 047d12h 047d13h 047d14h 047d15h can0 mailbox 17: data length xxh 047d16h can0 mailbox 17: data field xxxx xxxx xxxx xxxxh 047d17h 047d18h 047d19h 047d1ah 047d1bh 047d1ch 047d1dh 047d1eh can0 mailbox 17: time stamp xxxxh 047d1fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 67 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.49 sfr list (49) address register symbol reset value 047d20h can0 mailbox 18: message identifier c0mb18 xxxx xxxxh 047d21h 047d22h 047d23h 047d24h 047d25h can0 mailbox 18: data length xxh 047d26h can0 mailbox 18: data field xxxx xxxx xxxx xxxxh 047d27h 047d28h 047d29h 047d2ah 047d2bh 047d2ch 047d2dh 047d2eh can0 mailbox 18: time stamp xxxxh 047d2fh 047d30h can0 mailbox 19: message identifier c0mb19 xxxx xxxxh 047d31h 047d32h 047d33h 047d34h 047d35h can0 mailbox 19: data length xxh 047d36h can0 mailbox 19: data field xxxx xxxx xxxx xxxxh 047d37h 047d38h 047d39h 047d3ah 047d3bh 047d3ch 047d3dh 047d3eh can0 mailbox 19: time stamp xxxxh 047d3fh 047d40h can0 mailbox 20: message identifier c0mb20 xxxx xxxxh 047d41h 047d42h 047d43h 047d44h 047d45h can0 mailbox 20: data length xxh 047d46h can0 mailbox 20: data field xxxx xxxx xxxx xxxxh 047d47h 047d48h 047d49h 047d4ah 047d4bh 047d4ch 047d4dh 047d4eh can0 mailbox 20: time stamp xxxxh 047d4fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 68 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.50 sfr list (50) address register symbol reset value 047d50h can0 mailbox 21: message identifier c0mb21 xxxx xxxxh 047d51h 047d52h 047d53h 047d54h 047d55h can0 mailbox 21: data length xxh 047d56h can0 mailbox 21: data field xxxx xxxx xxxx xxxxh 047d57h 047d58h 047d59h 047d5ah 047d5bh 047d5ch 047d5dh 047d5eh can0 mailbox 21: time stamp xxxxh 047d5fh 047d60h can0 mailbox 22: message identifier c0mb22 xxxx xxxxh 047d61h 047d62h 047d63h 047d64h 047d65h can0 mailbox 22: data length xxh 047d66h can0 mailbox 22: data field xxxx xxxx xxxx xxxxh 047d67h 047d68h 047d69h 047d6ah 047d6bh 047d6ch 047d6dh 047d6eh can0 mailbox 22: time stamp xxxxh 047d6fh 047d70h can0 mailbox 23: message identifier c0mb23 xxxx xxxxh 047d71h 047d72h 047d73h 047d74h 047d75h can0 mailbox 23: data length xxh 047d76h can0 mailbox 23: data field xxxx xxxx xxxx xxxxh 047d77h 047d78h 047d79h 047d7ah 047d7bh 047d7ch 047d7dh 047d7eh can0 mailbox 23: time stamp xxxxh 047d7fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 69 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.51 sfr list (51) address register symbol reset value 047d80h can0 mailbox 24: message identifier c0mb24 xxxx xxxxh 047d81h 047d82h 047d83h 047d84h 047d85h can0 mailbox 24: data length xxh 047d86h can0 mailbox 24: data field xxxx xxxx xxxx xxxxh 047d87h 047d88h 047d89h 047d8ah 047d8bh 047d8ch 047d8dh 047d8eh can0 mailbox 24: time stamp xxxxh 047d8fh 047d90h can0 mailbox 25: message identifier c0mb25 xxxx xxxxh 047d91h 047d92h 047d93h 047d94h 047d95h can0 mailbox 25: data length xxh 047d96h can0 mailbox 25: data field xxxx xxxx xxxx xxxxh 047d97h 047d98h 047d99h 047d9ah 047d9bh 047d9ch 047d9dh 047d9eh can0 mailbox 25: time stamp xxxxh 047d9fh 047da0h can0 mailbox 26: message identifier c0mb26 xxxx xxxxh 047da1h 047da2h 047da3h 047da4h 047da5h can0 mailbox 26: data length xxh 047da6h can0 mailbox 26: data field xxxx xxxx xxxx xxxxh 047da7h 047da8h 047da9h 047daah 047dabh 047dach 047dadh 047daeh can0 mailbox 26: time stamp xxxxh 047dafh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 70 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.52 sfr list (52) address register symbol reset value 047db0h can0 mailbox 27: message identifier c0mb27 xxxx xxxxh 047db1h 047db2h 047db3h 047db4h 047db5h can0 mailbox 27: data length xxh 047db6h can0 mailbox 27: data field xxxx xxxx xxxx xxxxh 047db7h 047db8h 047db9h 047dbah 047dbbh 047dbch 047dbdh 047dbeh can0 mailbox 27: time stamp xxxxh 047dbfh 047dc0h can0 mailbox 28: message identifier c0mb28 xxxx xxxxh 047dc1h 047dc2h 047dc3h 047dc4h 047dc5h can0 mailbox 28: data length xxh 047dc6h can0 mailbox 28: data field xxxx xxxx xxxx xxxxh 047dc7h 047dc8h 047dc9h 047dcah 047dcbh 047dcch 047dcdh 047dceh can0 mailbox 28: time stamp xxxxh 047dcfh 047dd0h can0 mailbox 29: message identifier c0mb29 xxxx xxxxh 047dd1h 047dd2h 047dd3h 047dd4h 047dd5h can0 mailbox 29: data length xxh 047dd6h can0 mailbox 29: data field xxxx xxxx xxxx xxxxh 047dd7h 047dd8h 047dd9h 047ddah 047ddbh 047ddch 047dddh 047ddeh can0 mailbox 29: time stamp xxxxh 047ddfh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 71 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.53 sfr list (53) address register symbol reset value 047de0h can0 mailbox 30: message identifier c0mb30 xxxx xxxxh 047de1h 047de2h 047de3h 047de4h 047de5h can0 mailbox 30: data length xxh 047de6h can0 mailbox 30: data field xxxx xxxx xxxx xxxxh 047de7h 047de8h 047de9h 047deah 047debh 047dech 047dedh 047deeh can0 mailbox 30: time stamp xxxxh 047defh 047df0h can0 mailbox 31: message identifier c0mb31 xxxx xxxxh 047df1h 047df2h 047df3h 047df4h 047df5h can0 mailbox 31: data length xxh 047df6h can0 mailbox 31: data field xxxx xxxx xxxx xxxxh 047df7h 047df8h 047df9h 047dfah 047dfbh 047dfch 047dfdh 047dfeh can0 mailbox 31: time stamp xxxxh 047dffh 047e00h can0 mask register 0 c0mkr0 xxxx xxxxh 047e01h 047e02h 047e03h 047e04h can0 mask register 1 c0mkr1 xxxx xxxxh 047e05h 047e06h 047e07h 047e08h can0 mask register 2 c0mkr2 xxxx xxxxh 047e09h 047e0ah 047e0bh 047e0ch can0 mask register 3 c0mkr3 xxxx xxxxh 047e0dh 047e0eh 047e0fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 72 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.54 sfr list (54) address register symbol reset value 047e10h can0 mask register 4 c0mkr4 xxxx xxxxh 047e11h 047e12h 047e13h 047e14h can0 mask register 5 c0mkr5 xxxx xxxxh 047e15h 047e16h 047e17h 047e18h can0 mask register 6 c0mkr6 xxxx xxxxh 047e19h 047e1ah 047e1bh 047e1ch can0 mask register 7 c0mkr7 xxxx xxxxh 047e1dh 047e1eh 047e1fh 047e20h can0 fifo receive id compare register 0 c0fidcr0 xxxx xxxxh 047e21h 047e22h 047e23h 047e24h can0 fifo receive id compare register 1 c0fidcr1 xxxx xxxxh 047e25h 047e26h 047e27h 047e28h can0 mask invalid register c0mkivlr xxxx xxxxh 047e29h 047e2ah 047e2bh 047e2ch can0 mailbox interrupt enable register c0mier xxxx xxxxh 047e2dh 047e2eh 047e2fh 047e30h 047e31h 047e32h 047e33h 047e34h 047e35h 047e36h 047e37h 047e38h 047e39h 047e3ah 047e3bh 047e3ch 047e3dh 047e3eh 047e3fh 047e40h to 047f1fh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 73 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.55 sfr list (55) address register symbol reset value 047f20h can0 message control register 0 c0mctl0 00h 047f21h can0 message control register 1 c0mctl1 00h 047f22h can0 message control register 2 c0mctl2 00h 047f23h can0 message control register 3 c0mctl3 00h 047f24h can0 message control register 4 c0mctl4 00h 047f25h can0 message control register 5 c0mctl5 00h 047f26h can0 message control register 6 c0mctl6 00h 047f27h can0 message control register 7 c0mctl7 00h 047f28h can0 message control register 8 c0mctl8 00h 047f29h can0 message control register 9 c0mctl9 00h 047f2ah can0 message control register 10 c0mctl10 00h 047f2bh can0 message control register 11 c0mctl11 00h 047f2ch can0 message control register 12 c0mctl12 00h 047f2dh can0 message control register 13 c0mctl13 00h 047f2eh can0 message control register 14 c0mctl14 00h 047f2fh can0 message control register 15 c0mctl15 00h 047f30h can0 message control register 16 c0mctl16 00h 047f31h can0 message control register 17 c0mctl17 00h 047f32h can0 message control register 18 c0mctl18 00h 047f33h can0 message control register 19 c0mctl19 00h 047f34h can0 message control register 20 c0mctl20 00h 047f35h can0 message control register 21 c0mctl21 00h 047f36h can0 message control register 22 c0mctl22 00h 047f37h can0 message control register 23 c0mctl23 00h 047f38h can0 message control register 24 c0mctl24 00h 047f39h can0 message control register 25 c0mctl25 00h 047f3ah can0 message control register 26 c0mctl26 00h 047f3bh can0 message control register 27 c0mctl27 00h 047f3ch can0 message control register 28 c0mctl28 00h 047f3dh can0 message control register 29 c0mctl29 00h 047f3eh can0 message control register 30 c0mctl30 00h 047f3fh can0 message control register 31 c0mctl31 00h x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 74 of 112 jan 27, 2012 r32c/121 group 4. specia l function registers (sfrs) table 4.56 sfr list (56) address register symbol reset value 047f40h can0 control register c0ctlr 0000 0101b 047f41h 0000 0000b 047f42h can0 status register c0str 0000 0101b 047f43h 0000 0000b 047f44h can0 bit configuration register c0bcr 00 0000h 047f45h 047f46h 047f47h can0 clock select register c0clkr 000x 0000b 047f48h can0 receive fifo control register c0rfcr 1000 0000b 047f49h can0 receive fifo pointer control register c0rfpcr xxh 047f4ah can0 transmit fifo c ontrol register c0tfcr 1000 0000b 047f4bh can0 transmit fifo pointer control register c0tfpcr xxh 047f4ch can0 error interrupt enable register c0eier 00h 047f4dh can0 error interrupt factor judge register c0eifr 00h 047f4eh can0 receive error count register c0recr 00h 047f4fh can0 transmit error count register c0tecr 00h 047f50h can0 error code store register c0ecsr 00h 047f51h can0 channel search support register c0cssr xxh 047f52h can0 mailbox search status register c0mssr 1000 0000b 047f53h can0 mailbox search mode register c0msmr 0000 0000b 047f54h can0 time stamp register c0tsr 0000h 047f55h 047f56h can0 acceptance filter support register c0afsr xxxxh 047f57h 047f58h can0 test control register c0tcr 00h 047f59h 047f5ah 047f5bh 047f5ch 047f5dh 047f5eh 047f5fh 047f60h to 047fffh 048000h to 04ffffh x: undefined blanks are reserved. no access is allowed.
r01ds0070ej0120 rev.1.20 page 75 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics 5. electrical characteristics note: 1. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ra ting conditions for ex tended periods may affe ct device reliability. table 5.1 absolute maximum ratings (1) symbol characteristic condition value unit v cc supply voltage v cc = av cc -0.3 to 6.0 v av cc analog supply voltage v cc = av cc -0.3 to 6.0 v v i input voltage xin, reset , cnvss, nsd, v ref , p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 -0.3 to v cc + 0.3 v v o output voltage xout, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 -0.3 to v cc + 0.3 v p d power consumption t a = 25c 500 mw ? operating temperature range -40 to 125 c t stg storage temperature range -65 to 150 c
r01ds0070ej0120 rev.1.20 page 76 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. v ih and v il for p8_7 are specified for p8_7 as a programmable port. these values are not applicable for p8_7 as xcin. table 5.2 operating conditions (1/6) (1) symbol characteristic value unit min. typ. max. v cc digital supply voltage 3.0 5.0 5.5 v av cc analog supply voltage v cc v v ref reference voltage 3.0 v cc v v ss digital ground voltage 0v av ss analog ground voltage 0v dv cc /dt v cc ramp up rate (v cc < 2.0 v) 0.05 v/ms v ih high level input voltage xin, reset , cnvss, nsd 0.8 v cc v cc v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (2) , p9_1, p9_3 to p9_7, p10_0 to p10_7 0.7 v cc v cc v v il low level input voltage xin, reset , cnvss, nsd 0 0.2 v cc v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (2) , p9_1, p9_3 to p9_7, p10_0 to p10_7 0 0.3 v cc v t opr operating temperature range j version -40 85 c l version -40 105 c k version -40 125 c
r01ds0070ej0120 rev.1.20 page 77 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. this value should be met with due consideration to the following conditi ons: operating temperature, dc bias, aging, etc. table 5.3 operating conditions (2/6) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value (2) unit min. typ. max. c vdc decoupling capacitance for voltage regulator inter-pin voltage: 1.5 v 2.4 10.0 f
r01ds0070ej0120 rev.1.20 page 78 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. the following conditions should be satisfied: ? the sum of i ol(peak) of ports p0, p1, p2, p8_6, p8_7, p9, and p10 is 80 ma or less. ? the sum of i ol(peak) of ports p3, p4, p5, p6, p7, an d p8_0 to p8_4 is 80 ma or less. ? the sum of i oh(peak) of ports p1 and p2 is -40 ma or less. ? the sum of i oh(peak) of ports p0 and p10 is -40 ma or less. ? the sum of i oh(peak) of ports p3, p4, p5, and p6 is -40 ma or less. ? the sum of i oh(peak) of ports p7, p8, and p9 is -40 ma or less. 3. average value within 100 ms. table 5.4 operating conditions (3/6) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. i oh (peak) high level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 -10.0 ma i oh (avg) high level average output current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 -5.0 ma i ol (peak) low level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 10.0 ma i ol (avg) low level average output current (3) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 5.0 ma
r01ds0070ej0120 rev.1.20 page 79 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.1 clock cycle time table 5.5 operating conditions (4/6) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. f (xin) main clock osc illator frequency 48mhz f (xref) reference clock frequency 24mhz f (pll) pll clock oscilla tor frequency 96 144 mhz f (base) base clock frequency 64 mhz t c(base) base clock cycle time 15.625 ns f (cpu) cpu operating frequency 64 mhz t c (cpu) cpu clock cycle time 15.625 ns f (bclk) peripheral bus clock operating frequency 32 mhz t c (bclk) peripheral bus clock cycle time 31.25 ns f (per) peripheral clock source frequency 32 mhz f (xcin) sub clock oscillator frequency 32.768 50 khz base clock (internal signal) t c(base) peripheral bus clock (internal signal) t c(bclk) cpu clock (internal signal) t c(cpu)
r01ds0070ej0120 rev.1.20 page 80 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. these conditions are applicable when each port is designated as input. table 5.6 operating conditions (5/6) (v cc = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) (1, 2) symbol characteristic measurement condition value unit min. typ. max. i ic(h) high input injection current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_5, p7_7, p8_0 to p8_5, p9_3 to p9_6, p10_0top10_7 v i > v cc 2ma i ic(l) low input injection current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_5, p7_7, p8_0 to p8_5, p9_3 to p9_6, p10_0top10_7 v i < v ss -2 ma |i ic | total injection current 20 ma
r01ds0070ej0120 rev.1.20 page 81 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.2 ripple waveform table 5.7 operating conditions (6/6) (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. v r(vcc) allowable ripple voltage v cc = 5.0 v 0.5 vp-p v cc = 3.0 v 0.3 vp-p dv r(vcc) /dt ripple voltage gradient v cc = 5.0 v 0.3 v/ms v cc = 3.0 v 0.3 v/ms f r(vcc) allowable ripple frequency 10 khz v cc 1 / f r(vcc) v r(vcc)
r01ds0070ej0120 rev.1.20 page 82 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics notes: 1. program/erase definition this value represents the number of erasures per block. when the number of program and erase cycles is n, each block can be erased n times. for example, if a 4-word write is performed in 512 different addresses in the 4-kbyte block a and then the block is erased, this is counted as a single program/erase operation. however, the same address cannot be written to more than once per erasure (overwrite disabled). 2. data retention includes periods when no supply voltage is applied and no clock is provided. 3. this data retention includes 3000 hours in t a = 125c and 7000 hours in t a = 85c. 4. contact a renesas electronics sales office for data retention times other than the above condition. table 5.8 electrical charac teristics of flash memory (v cc = 3.0 to 5.5 v, v ss =0v, and ta=t opr , unless otherwise noted) symbol characteristic value unit min. typ. max. ? program and erase cycles (1) program area 1000 cycles data area 10000 cycles ? 4-word program time program area 150 900 s data area 300 1700 s ? lock bit program time program area 70 500 s data area 140 1000 s ? block erasure time 4-kbyte block 0.12 3.0 s 32-kbyte block 0.17 3.0 s 64-kbyte block 0.20 3.0 s ? data retention (2) t a = 55c (3, 4) 20 years
r01ds0070ej0120 rev.1.20 page 83 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics notes: 1. program/erase definition this value represents the number of erasure per block. when the number of program and erase cycles is n, each block can be erased n times. for example, if a word write is performed in 16 different addresses in a block and then the block is erased, this is counted as a single program/erase operation. however, the same address cannot be written to more than once per erasure (overwrite disabled). 2. data retention includes periods when no supply voltage is applied and no clock is provided. 3. this data retention includes 3000 hours in t a = 125c and 7000 hours in t a = 85c. figure 5.3 power supply circuit timing table 5.9 electrical ch aracteristics of e 2 dataflash (v cc = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic value unit min. typ. max. ? program and erase cycles (1) 100000 cycles ? word program time 100 2000 s ? block erasure time 32 byte block 15 200 ms t ps flash memory circuit st art-up stabilization time 35 50 s ? data retention (2) t a = 55c (3, 4) 20 years 4. contact a renesas electronics sales office for data retention times other than the above condition. table 5.10 power supply circ uit timing characteristics (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. t d(p-r) internal power supply start-up stabilization time after the main power supply is turned on 2ms t d(p-r) v cc pll oscillator- output waveform internal power supply start-up stabilization time after the main power supply is turned on recommended operating voltage t d(p-r) supply voltage for internal logic
r01ds0070ej0120 rev.1.20 page 84 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics notes: 1. this value is the deviation from target frequency. 2. this value is applicable only when the main clock osc illation is stable. 3. this value is the time until the pl f1 bit in the pls register becomes 1. table 5.11 electrical characteristics of voltage regulator for internal logic (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. v vdc1 output voltage 1.5 v table 5.12 electrical characteri stics of low voltage detector (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. vdet detected voltage error 0.2 v vdet(r)-vdet(f) hysteresis width 0 v ? self-consuming current v cc = 5.0 v, low voltage detector enabled 4a t d(e-a) operation start time of low voltage detector 150 s table 5.13 electrical char acteristics of oscillator (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. f so(pll) pll clock self-osc illation frequency 35 50 80 mhz | f lock | lock detection (1) 2% | f unlock | unlock detection (1) 2% t lock(pll) pll lock time (2, 3) f (xref) =4mhz 1ms t jitter(p-p) pll jitter period (p-p) 2.0 ns f (oco) on-chip oscillator frequency 94 125 156 khz
r01ds0070ej0120 rev.1.20 page 85 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics note: 1. the stop mode reco very time does not inclu de the main clock oscillation stabilization time. the cpu starts operating before th e oscillator is stabilized. figure 5.4 clock circuit timing table 5.14 electrical characte ristics of clock circuitry (v cc = 3.0 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. t rec(wait) recovery time from wait mode to low power mode 225 s t rec(stop) recovery time from stop mode (1) 225 s t rec(stop) interrupt for exiting stop mode cpu clock main clock oscillator output on-chip oscillator output sub clock oscillator output on-chip oscillator output t rec(wait) interrupt for exiting wait mode cpu clock recovery time from stop mode t rec(stop) recovery time from wait mode to low power mode t rec(wait)
r01ds0070ej0120 rev.1.20 page 86 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics timing requirements (v cc = 3.0 to 5.5 v, v ss = 0 v, and ta = t opr , unless otherwise noted) figure 5.5 flash memory cpu rewrite mode timing table 5.15 flash memory cpu rewrite mode timing symbol characteristics value unit min. max. t cr read cycle time 200 ns t su(s-r) chip-select setup time before read 200 ns t h(r-s) chip-select hold time after read 0ns t su(a-r) address setup time before read 200 ns t h(r-a) address hold time after read 0ns t w(r) read pulse width 100 ns t cw write cycle time 200 ns t su(s-w) chip-select setup time before write 0ns t h(w-s) chip-select hold time after write 30 ns t su(a-w) address setup time before write 0ns t h(w-a) address hold time after write 30 ns t w(w) write pulse width 50 ns chip select address rd t h(r-s) read cycle t w(r) t su(s-r) t h(r-a) t su(a-r) write cycle chip select address wr t h(w-s) t w(w) t su(s-w) t h(w-a) t su(a-w) t cw t cr
r01ds0070ej0120 rev.1.20 page 87 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v table 5.16 electrical characteristics (1/3) (v cc = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 64 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i oh = -5 ma v cc - 2.0 v cc v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i oh = -200 a v cc - 0.3 v cc v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i ol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i ol = 200 a 0.45 v
r01ds0070ej0120 rev.1.20 page 88 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v table 5.17 electrical characteristics (2/3) (v cc = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 64 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis nmi , int0 to int5 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts4 , clk0 to clk4, rxd0 to rxd4, scl0 to scl2, sda0 to sda2, ss0 to ss2 , srxd0 to srxd2, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, scs0 to scs2 , ssck0 to ssck2, ssi0 to ssi2, sso0 to sso2, lin0in, lin1in, can0in, can1in, can0wu , can1wu 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 5 v 1.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 0 v -1.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 0 v 30 50 170 k r f xin feedback resistor xin 1.5 m r f xcin feedback resistor xcin 15 m
r01ds0070ej0120 rev.1.20 page 89 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v table 5.18 electrical characteristics (3/3) (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characterist ic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =64mhz, f (bclk) =32mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 36 60 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 7ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 1.2 ma f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 220 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 230 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 960 1600 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8140a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a stopped: all clocks, main regulator: shutdown, t a = 85c 400 a stopped: all clocks, main regulator: shutdown, t a = 105c 1200 a stopped: all clocks, main regulator: shutdown, t a = 125c 2000 a
r01ds0070ej0120 rev.1.20 page 90 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v table 5.19 a/d conversion characteristics (v cc =av cc =v ref =4.2to5.5v, v ss =av ss =0v, t a =t opr , and f (bclk) = 32 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc 10 bits ? absolute error v ref = v cc = 5 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 3 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc = 5 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 3 lsb external op-amp connection mode 7 lsb dnl differential non-linearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc 420k t conv conversion time (10 bits) ad = 16 mhz, with sample and hold function 2.06 s ad = 16 mhz, without sample and hold function 3.69 s t conv conversion time (8 bits) ad = 16 mhz, with sample and hold function 1.75 s ad = 16 mhz, without sample and hold function 3.06 s t samp sampling time ad = 16 mhz 0.188 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 16 mhz with sample and hold function 1 16 mhz r pu(ast) pull-up resistor for open- circuit detection 51015k r pd(ast) pull-down resistor for open-circuit detection 51015k
r01ds0070ej0120 rev.1.20 page 91 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unu sed converter is set to 00h. the resistor ladder for the a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.20 d/a conversion characteristics (v cc =av cc =v ref =4.2to5.5v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current see note 1 1.5 ma
r01ds0070ej0120 rev.1.20 page 92 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.21 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 125 250 ns t w(xh) external clock input high level pulse width 50 ns t w(xl) external clock input low level pulse width 50 ns t r (x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 %
r01ds0070ej0120 rev.1.20 page 93 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.22 timer a input (counting input in event counter mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.23 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 400 ns t w (tah) taiin input high level pulse width 180 ns t w (tal) taiin input low level pulse width 180 ns table 5.24 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.25 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.26 timer a input (increment/decrement switching input in event counter mode) symbol characteristic value unit min. max. t c (up) taiout input clock cycle time 2000 ns t w (uph) taiout input high level pulse width 1000 ns t w (upl) taiout input low level pulse width 1000 ns t su (up-tin) taiout input setup time 400 ns t h (tin-up) taiout input hold time 400 ns
r01ds0070ej0120 rev.1.20 page 94 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.27 timer b input (counting input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time (one edge counting) 200 ns t w (tbh) tbiin input high level pulse width (one edge counting) 80 ns t w (tbl) tbiin input low level pulse width (one edge counting) 80 ns t c (tb) tbiin input clock cycle ti me (both edges counting) 200 ns t w (tbh) tbiin input high level pulse width (both edges counting) 80 ns t w (tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.28 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns table 5.29 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns
r01ds0070ej0120 rev.1.20 page 95 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the values are applied in case the filtering function is disabled. table 5.30 serial interface symbol characteristic value unit min. max. t c (ck) clki input clock cycle time 200 ns t w (ckh) clki input high level pulse width 80 ns t w (ckl) clki input low level pulse width 80 ns t su (d-c) rxdi input setup time 80 ns t h (c-d) rxdi input hold time 90 ns table 5.31 a/d trigger input symbol characteristic value unit min. max. t w (adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w (adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.32 external interrupt inti input symbol characteristic value unit min. max. t w (inh) inti input high level pulse width (1) edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width (1) edge sensitive 250 ns level sensitive t c (cpu) + 200 ns 3 ad --------- -
r01ds0070ej0120 rev.1.20 page 96 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v timing requirements (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.33 serial bus interface symbol characteristic value unit min. max. f (ssck) sscki frequency 4mhz t c(ssck) sscki clock cycle time 250 ns t w(ssckh) sscki input high level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t w(ssckl) sscki input low level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t r(ssck) sscki input rising time 1s t f(ssck) sscki input falling time 1s t su(scs-ssck) scsi input setup time t c(bclk) + 50 ns t h(ssck-scs) scsi input hold time t c(bclk) + 50 ns t su(ssi-ssck) ssi input setup time 80 ns t h(ssck-ssi) ssi input hold time 10 ns t su(sso-ssck) sso input setup time 80 ns t h(ssck-sso) sso input hold time 20 ns
r01ds0070ej0120 rev.1.20 page 97 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =5v switching characteristics (v cc = 4.2 to 5.5 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.34 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.35 serial bus interface symbol characteristic measurement condition value unit min. max. t w(ssckh) sscki output high level pulse width refer to figure 5.6 0.35 t c(ssck) 0.6 t c(ssck) ns t w(ssckl) sscki output low level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t r(ssck) sscki output rising time 20 ns t f(ssck) sscki output falling time 20 ns t d(scs-ssck) sscki output delay time for scsi 0.5 t c(ssck) + 20 ns t d(ssck-scs) scsi output delay time for sscki 0.5 t c(ssck) - 20 ns t en(scs-sso) ssoi output enable time 1.5 t c(bclk) + 100 ns t dis(scs-sso) ssoi output disable time 1.5 t c(bclk) + 100 ns t en(scs-ssi) ssii output enable time 1.5 t c(bclk) + 100 ns t dis(scs-ssi) ssii output disable time 1.5 t c(bclk) + 100 ns t d(ssck-sso) ssoi output delay time for sscki 30 ns t d(ssck-ssi) ssii output delay time for sscki 85 ns t rec(scs) scsi output high level period in continuous transmission 0.625 t c(ssck) ns
r01ds0070ej0120 rev.1.20 page 98 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v table 5.36 electrical ch aracteristics (1/3) (v cc = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 64 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i oh = -1 ma v cc - 0.6 v cc v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i ol = 1 ma 0.5 v
r01ds0070ej0120 rev.1.20 page 99 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v table 5.37 electrical ch aracteristics (2/3) (v cc = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 64 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis nmi , int0 to int5 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts4 , clk0 to clk4, rxd0 to rxd4, scl0 to scl2, sda0 to sda2, ss0 to ss2 , srxd0tosrxd2, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, scs0 to scs2 , ssck0 to ssck2, ssi0 to ssi2, sso0 to sso2, lin0in, lin1in, can0in, can1in, can0wu , can1wu 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 3.3 v 1.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 0 v -1.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 v i = 0 v 50 100 500 k r f xin feedback resistor xin 3m r f xcin feedback resistor xcin 25 m
r01ds0070ej0120 rev.1.20 page 100 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v table 5.38 electrical characteristics (3/3) (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) symbol characte ristic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =64mhz, f (bclk) =32mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 36 60 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 7ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 670 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 180 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 190 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) = 8 mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 500 900 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8 140 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a stopped: all clocks, main regulator: shutdown, t a = 85c 400 a stopped: all clocks, main regulator: shutdown, t a = 105c 1200 a stopped: all clocks, main regulator: shutdown, t a = 125c 2000 a
r01ds0070ej0120 rev.1.20 page 101 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v table 5.39 a/d conversion characteristics (v cc =av cc =v ref =3.0to3.6v, v ss =av ss =0v, t a =t opr , and f (bclk) = 32 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc 10 bits ? absolute error v ref = v cc = 3.3 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 5 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc = 3.3 v an_0toan_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 5 lsb external op-amp connection mode 7 lsb dnl differential non- linearity error v ref = v cc = 3.3 v 1 lsb ? offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc 420k t conv conversion time (10 bits) ad = 10 mhz, with sample and hold function 3.3 s t conv conversion time (8 bits) ad = 10 mhz, with sample and hold function 2.8 s t samp sampling time ad = 10 mhz 0.3 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 10 mhz with sample and hold function 1 10 mhz r pu(ast) pull-up resistor for open-circuit detection 51015k r pd(ast) pull-down resistor for open-circuit detection 51015k
r01ds0070ej0120 rev.1.20 page 102 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unu sed converter is set to 00h. the resistor ladder for the a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.40 d/a conversion characteristics (v cc =av cc =v ref =3.0to3.6v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current see note 1 1.0 ma
r01ds0070ej0120 rev.1.20 page 103 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.41 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 125 250 ns t w(xh) external clock input high level pulse width 50 ns t w(xl) external clock input low level pulse width 50 ns t r(x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 %
r01ds0070ej0120 rev.1.20 page 104 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.42 timer a input (counting input in event counter mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.43 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 400 ns t w(tah) taiin input high level pulse width 180 ns t w(tal) taiin input low level pulse width 180 ns table 5.44 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.45 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w(tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.46 timer a input (increment/decrement switching input in event counter mode) symbol characteristic value unit min. max. t c(up) taiout input clock cycle time 2000 ns t w(uph) taiout input high level pulse width 1000 ns t w(upl) taiout input low level pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns
r01ds0070ej0120 rev.1.20 page 105 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.47 timer b input (counting input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time (one edge counting) 200 ns t w(tbh) tbiin input high level pulse width (one edge counting) 80 ns t w(tbl) tbiin input low level pulse width (one edge counting) 80 ns t c(tb) tbiin input clock cycle ti me (both edges counting) 200 ns t w(tbh) tbiin input high level pulse width (both edges counting) 80 ns t w(tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.48 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns table 5.49 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns
r01ds0070ej0120 rev.1.20 page 106 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) note: 1. the values are applied in case filtering function is disabled. table 5.50 serial interface symbol characteristic value unit min. max. t c(ck) clki input clock cycle time 200 ns t w(ckh) clki input high level pulse width 80 ns t w(ckl) clki input low level pulse width 80 ns t su(d-c) rxdi input setup time 80 ns t h(c-d) rxdi input hold time 90 ns table 5.51 a/d trigger input symbol characteristic value unit min. max. t w(adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w(adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.52 external interrupt inti input symbol characteristic value unit min. max. t w(inh) inti input high level pulse width (1) edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width (1) edge sensitive 250 ns level sensitive t c (cpu) + 200 ns 3 ad --------- -
r01ds0070ej0120 rev.1.20 page 107 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v timing requirements (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.53 serial bus interface symbol characteristic value unit min. max. f (ssck) sscki frequency 4mhz t c(ssck) sscki clock cycle time 250 ns t w(ssckh) sscki input high level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t w(ssckl) sscki input low level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t r(ssck) sscki input rising time 1s t f(ssck) sscki input falling time 1s t su(scs-ssck) scsi input setup time t c(bclk) + 50 ns t h(ssck-scs) scsi input hold time t c(bclk) + 50 ns t su(ssi-ssck) ssi input setup time 100 ns t h(ssck-ssi) ssi input hold time 10 ns t su(sso-ssck) sso input setup time 100 ns t h(ssck-sso) sso input hold time 20 ns
r01ds0070ej0120 rev.1.20 page 108 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics v cc =3.3v switching characteristics (v cc = 3.0 to 3.6 v, v ss = 0 v, and t a =t opr , unless otherwise noted) table 5.54 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.55 serial bus interface symbol characteristic measurement condition value unit min. max. t w(ssckh) sscki output high level pulse width refer to figure 5.6 0.35 t c(ssck) 0.6 t c(ssck) ns t w(ssckl) sscki output low level pulse width 0.35 t c(ssck) 0.6 t c(ssck) ns t r(ssck) sscki output rising time 35 ns t f(ssck) sscki output falling time 35 ns t d(scs-ssck) sscki output delay time for scsi 0.5 t c(ssck) + 40 ns t d(ssck-scs) scsi output delay time for sscki 0.5 t c(ssck) - 40 ns t en(scs-sso) ssoi output enable time 1.5 t c(bclk) + 100 ns t dis(scs-sso) ssoi output disable time 1.5 t c(bclk) + 100 ns t en(scs-ssi) ssii output enable time 1.5 t c(bclk) + 100 ns t dis(scs-ssi) ssii output disable time 1.5 t c(bclk) + 100 ns t d(ssck-sso) ssoi output delay time for sscki 50 ns t d(ssck-ssi) ssii output delay time for sscki 120 ns t rec(scs) scsi output high level period in continuous transmission 0.625 t c(ssck) ns
r01ds0070ej0120 rev.1.20 page 109 of 112 jan 27, 2012 r32c/121 group 5. elec trical characteristics figure 5.6 switching characteri stic measurement circuit figure 5.7 external clock input timing 30 pf pin to be measured mcu xin t w(xh) t w(xl) t r(x) t f(x) t c(x)
r01ds0070ej0120 rev.1.20 page 110 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics figure 5.8 timing of peripheral functions taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input (in falling edge counting) taiout input (input for increment/ decrement switching) in event counter mode taiin input (in rising edge counting) t h(tin-up) tbiin input adtrg input t c(tb) t w(tbh) t w(tbl) t w(adl) clki t c(ck) t w(ckh) t w(ckl) txdi t d(c-q) t h(c-q) rxdi t su(d-c) t h(c-d) inti input t w(inl) t w(inh) nmi input two cpu clock cycles + 300 ns or more two cpu clock cycles + 300 ns or more t su(up-tin) t w(adh)
r01ds0070ej0120 rev.1.20 page 111 of 112 jan 27, 2012 r32c/121 group 5. electrical characteristics figure 5.9 timing of serial bus interface scsi (output) sscki (output) t d(scs-ssck) ssoi (output) t d(ssck-scs) sscki t w(ssckh) t w(ssckl) t c(ssck) t r(ssck) t f(ssck) t dis(scs-sso) cpos = 1 cpos = 0 sscki ssii / ssoi (output) t d(ssck-sso) cphs = 1 cpos = 1 cpos = 0 t d(ssck-sso) cphs = 0 t en(scs-sso) t d(ssck-ssi) t d(ssck-ssi) ssii / ssoi (input) cphs = 1 cphs = 0 t su(sso-ssck) t su(ssi-ssck) t h(ssck-sso) t h(ssck-ssi) t su(sso-ssck) t su(ssi-ssck) t h(ssck-sso) t h(ssck-ssi) scsi (input) sscki (input) t su(scs-ssck) t en(scs-ssi) ssii (output) t h(ssck-scs) cpos = 1 cpos = 0 t dis(scs-ssi) t rec(scs)
r01ds0070ej0120 rev.1.20 page 112 of 112 jan 27, 2012 r32c/121 group appendix 1. package dimensions appendix 1. package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e y s s
a- 1 revision history r32c/121 group datasheet rev. date description page summary 0.31 feb 14, 2008 ? initial release 0.50 jul 31, 2008 ? second edition released chapter 1 1 ? ?(mcus)? in line 1 of 1.1 added ? ?this specification? in ?notes to users? changed to ?specifications? 6? figure 1.2 modified 11-13 ? ?functional catego ry? and ?function? in tables 1.7 to 1.9 changed to ?function? and ?description?, respectively 11 ? expression ?internal logic voltage regulator? for ?connecting pins for decoupling capacitor? in table 1.7 changed to ?internal voltage? ? descriptions for ?i/o ports? and ?input port? in table 1.7 modified chapter 2 14, 15 ? ?interrupt table register? in figure 2.1 and 2.1.6 changed to ?interrupt vector table base register? 15, 16 ? descriptions for 2.1 revised chapter 3 18 ? descriptions for chapter 3 modified chapter 4 ? ? some ?sfr? pluralized 19 ? description for initial paragraph of chapter 4 modified 20, 21 ? ?dmai in terrupt? in tables 4.2 and 4.3 changed to ?dmai transfer complete interrupt? 36 ? reset value for pls in table 4.18 changed 42 ? ?dmai source select register j? in table 4.24 changed to ?dmai request source select register j? 74 ? addresses ?047f60h to 047fffh? and ?048000h to 04ffffh? added to table 4.56 chapter 5 75-110 ? this chapter newly added 1.10 mar 02, 2010 ? third edition released chapter 1. overview 3 ? modified description for ?flash memory? in table 1.2 4, 5 ? changed part numbers in table 1.3 and figure 1.1 11 ? changed expression ?a crystal oscillator? in table 1.7 to ?a crystal? chapter 2. cpu ? ? made minor text modifications to this chapter chapter 3. memory ? ? made minor text modifications to this chapter chapter 4. sfrs 19 ? changed hexadecimal format of reset values for registers ccr and fmcr in table 4.1 to binary 20, 21 ? changed register name ?uarti start/stop condition detection interrupt control register? in tables 4.2 and 4.3 to ?uarti start condition/stop condition detection interrupt control register?
a- 2 27 ? changed reset values ? xxxx xxxxb? and ?xxxx 000xb? for registers u3rb and u4rb in table 4.9 to ?xxxxh? 29 ? changed expression of register name ?xi register yi register? and register symbol ?xir, yir? in table 4.11 to ?xi register/yi register? and ?xir/yir?, respectively 34 ? changed hexadecimal format of reset values for registers pd0 to pd7, pd9, and pd10 in table 4.16 to binary 38-40 ? changed register name ?port pi_j port function select register? in tables 4.20 to 4.22 to ?port pi_j function select register? 42 ? changed register name ?dmai requ est source select register 1? in table 4.24 to ?dmai request source select register? ? changed register names ?wake-up/interrupt priority level control register 2? and ?wake-up/interrupt priority level control register 1? in table 4.24 to ?wake-up ipl setting register 2? and ?wake-up ipl setting register 1?, respectively 43 ? modified ?x? in reset values fo r unassigned bits to ?0? for the following registers in table 4.25 : lcw, lbrg, lmd0, lbrk, lspc, lrfc, lsc, ltc, lst, and lest 60, 74 ? modified reset value ?00h? for c1clkr in table 4.42 and c0clkr in table 4.56 to ?000x 0000b? chapter 5. electrical characteristics ? ? made minor text modifications to this chapter 76 ? added description of dv cc /dt to table 5.2 77 ? added note 2 to table 5.3 78 ? corrected a typo ?pots? in line 2 of note 2 for table 5.4 to ?ports? 82 ? deleted specification of ?t ps ? from table 5.8 83 ? corrected a typo ?32 kbyte block? in table 5.9 to ?32 byte block? ? deleted the measurement condition from table 5.10 84 ? changed voltage condition for table 5.12 from ?vcc = 3.0 to 5.5 v? to ?vcc = 4.2 to 5.5 v? ? changed the following expressions in table 5.13 : ?pll frequency synthesizer stabilizat ion time? to ?pll lock time? and ?t osc(pll) ? to ?t lock(pll) ?; added the measurement condition and note 3 for t lock(pll) ? newly added two characteristics: ?lock detection? and ?unlock detection? and note 1 ? changed maximum value for f so(pll) in table 5.13 from ?65? to ?80? 85 ? changed the order of description of t rec(stop) and t rec(wait) in table 5.14 and figure 5.4 88, 99 ? deleted ?p8_5? from ?characteri stic? of ?pull-up resistor? in tables 5.17 and 5.37 89, 100 ? changed expression ?running? for ?measurement condition? in tables 5.18 and 5.38 to ?active?; added ?xin? as ?active? to first, third, and sixth rows of respective tables 90 ? modified expression ?sample time? for ?characteristics? in table 5.19 to ?sampling time? revision history r32c/121 group datasheet rev. date description page summary
a- 3 90, 101 ? modified minimum value ?0.125? for ad in tables 5.19 and 5.39 to ?0.25? 95 ? corrected a typo ?th(c-q)? in table 5.30 to ?th(c-d)? 95, 106 ? changed minimum value for ?tw (adh) ? in tables 5.31 and 5.51 from ?2/ ad ? to ?3/ ad ? 96, 107 ? corrected a typo ?s scki input falling time? in tables 5.33 and 5.53 to ?sscki input falling time? 97, 108 ? modified description ?txdi hold time? in tables 5.34 and 5.54 to ?txdi output hold time? 99 ? changed measurement condition for ?high level input current? in table 5.37 , from ?vi = 3 v? to ?vi = 3.3 v? 103 ? corrected typos ?t w (h)?, ?t w (l)?, ?t r ?, and ?t f ? in table 5.41 to ?t w (xh)?, ?t w (xl)?, ?t r (x)?, and ?t f (x)?, respectively 1.20 jan 27, 2012 ? fourth edition released this manual in general ? ? applied new renesas templates and formats to the manual ? changed company name to ?renesas electronics corporation? and changed related descriptions due to business merger of renesas technology corporation and nec electronic corporation ? changed document number ?rej03b0237-0110? to ?r01ds0070ej0120? ? modified the following expressions: ?version j?, ?version l?, and ?version k? to ?j version?, ?l vers ion?, and ?k version?, respectively (under chapters 1 and 5) chapter 1. overview ? ? modified wording and enhanced description in this chapter 2 ? modified expressions ?main cloc k oscillator stop/re-oscillation detection? and ?inputs/outputs? in table 1.1 to ?main clock oscillator stop/restart detection? and ?i/o ports?, respectively 4 ? completed all ?under development? phases in table 1.3 7 ? changed order of signals in figure 1.3 8 ? changed orders of timer pins ?ta4in/ u /ta3out? and ?tb5in/ ta0in? in table 1.4 to ?ta3out/ta4in/ u ? and ?ta0in/tb5in?, respectively 11 ? modified expression ?fc? in table 1.7 to ?low speed clocks? chapter 2. cpu ? ? modified wording and enhanced description in this chapter 15 ? corrected a typo ?r3r0? in line 3 of 2.1.1 to ?r3r1? chapter 3. memory ? ? modified wording and enhanced description in this chapter chapter 4. sfrs ? ? made minor text modifications to this chapter 24, 26 ? changed hexadecimal format of reset values for registers g1bcr0 and g0bcr0 in tables 4.6 and 4.8 to binary; changed register name ?group i timer measurement prescaler register? to ?group i time measurement prescaler register? revision history r32c/121 group datasheet rev. date description page summary
a- 4 29 ? modified expression ?xy control register? in table 4.11 to ?x-y control register? 31 ? changed register names ?uart2 transmission/receive mode register? and ?increment/decrement counting select register? in table 4.13 to ?uart2 transmit/receive mode register? and ?increment/decrement select r egister?; changed hexadecimal format of reset valu es for registers tabsr , onsf, and trgsr to binary 38 ? corrected reset value ?x000 x000b? for ifs0 register in table 4.20 to ?x0x0 x000b? 42 ? changed register name ?external interrupt source select register 0? in table 4.24 to ?external interrupt request source select register 0? 57, 58, 71, 72 ? modified register name ?cani acceptance mask register k? in tables 4.39, 4.40, 4.53, and 4.54 to ?cani mask register k? 60, 74 ? modified register names ?cani reception error count register? and ?cani transmission error count register? in tables 4.42 and 4.56 to ?cani receive error count register? and ?cani transmit error count register?, resp ectively; corrected re set value ?xxxx xx00b? for registers c1msmr and c0msmr to ?0000 0000b? chapter 5. electrical characteristics ? ? modified wording and enhanced description in this chapter ? changed expression ?clock period? to ?clock cycle time? 82, 83 ? changed expression ?programming and erasure endurance? in tables 5.8 and 5.9 to ?program and erase cycles?; changed its unit ?times? in the table and note 1 to ?cycles? 86 ? changed expressions ? cs0 ? and ?a23 to a0, bc0 to bc3 ? in figure 5.5 to ?chip select? and ?address?, respectively 95, 106 ? corrected ?inti? in the title of tables 5.32 and 5.52 to ? inti ? appendix 1. package dimensions 112 ? added a seating plane to the drawing of package dimension all trademarks and registered trademarks ar e the property of their respective owners. revision history r32c/121 group datasheet rev. date description page summary
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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